N-Channel JFET - Model N-Channel JFET

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Semiconductor Devices

Description

The N-Channel JFET block uses the Shichman and Hodges equations to represent an N-Channel JFET using a model with the following structure:

G is the transistor gate, D is the transistor drain and S is the transistor source. The drain-source current, Ids, depends on the region of operation and whether the transistor is operating in normal or inverse mode.

In the preceding equations:

The currents in each of the diodes satisfy the exponential diode equation

Where:

The block models gate junction capacitance as a fixed gate-drain capacitance CGD and a fixed gate-source capacitance CGS. If you select Specify using equation parameters directly for the Parameterization parameter, you specify these values directly using the Gate-drain junction capacitance and Gate-source junction capacitance parameters. Otherwise, the block derives them from the Input capacitance Ciss and Reverse transfer capacitance Crss parameter values. The two parameterizations are related as follows:

Basic Assumptions and Limitations

The model is based on the following assumptions:

Dialog Box and Parameters

Main Tab

Parameterization

Select one of the following methods for block parameterization:

Gate reverse current I_gss

The reverse current that flows in the diode when the drain and source are short-circuited and a large negative gate-source voltage is applied. This parameter is only visible when you select Specify from a datasheet for the Parameterization parameter. The default value is -1 nA.

Saturated drain current I_dss

The current that flows when a large positive drain-source voltage is applied for a specified gate-source voltage. For a depletion-mode device, this gate-source voltage may be zero, in which case Idss may be referred to as the zero-gate voltage drain current. This parameter is only visible when you select Specify from a datasheet for the Parameterization parameter. The default value is 3 mA.

I_dss measurement point [V_gs V_ds]

A vector of the values of Vgs and Vds at which Idss is measured. Normally Vgs is zero. Vds should be greater than zero. This parameter is only visible when you select Specify from a datasheet for the Parameterization parameter. The default value is [ 0 15 ] V.

Small-signal parameters [g_fs g_os]

A vector of the values of gfs and gos. gfs is the forward transfer conductance, i.e. the conductance for a fixed drain-source voltage. gos is the output conductance, i.e. the conductance for a fixed gate-source voltage. This parameter is only visible when you select Specify from a datasheet for the Parameterization parameter. The default value is [ 3e+03 10 ] uS.

Small-signal measurement point [V_gs V_ds]

A vector of the values of Vgs and Vds at which gfs and gos are measured. Vds should be greater than zero. For depletion-mode devices, Vgs is typically zero. This parameter is only visible when you select Specify from a datasheet for the Parameterization parameter. The default value is [ 0 15 ] V.

Transconductance parameter

The derivative of drain current with respect to gate voltage. This parameter is only visible when you select Specify using equation parameters directly for the Parameterization parameter. The default value is 1e-04 A/V2.

Saturation current

The magnitude of the current that the ideal diode equation approaches asymptotically for very large reverse bias levels. This parameter is only visible when you select Specify using equation parameters directly for the Parameterization parameter. The default value is 1e-14 A.

Measurement temperature

The temperature for which the datasheet parameters are quoted. It is also the temperature at which the device is simulated. The default value is 25 C.

Threshold voltage

The gate-source voltage above which the transistor produces a nonzero drain current. For an enhancement device, Vt0 should be positive. For a depletion mode device, Vt0 should be negative. This parameter is only visible when you select Specify using equation parameters directly for the Parameterization parameter. The default value is -2 V.

Channel-length modulation

The channel-length modulation. This parameter is only visible when you select Specify using equation parameters directly for the Parameterization parameter. The default value is 0 1/V.

Ohmic Resistance Tab

Source ohmic resistance

The transistor source resistance. The default value is 0.1 Ω. The value must be greater than or equal to 0.

Drain ohmic resistance

The transistor drain resistance. The default value is 0.1 Ω. The value must be greater than or equal to 0.

Junction Capacitance Tab

Parameterization

Select one of the following methods for block parameterization:

Input capacitance Ciss

The gate-source capacitance with the drain shorted to the source. This parameter is only visible when you select Specify from a datasheet for the Model junction capacitance parameter. The default value is 4.5 pF.

Reverse transfer capacitance Crss

The drain-gate capacitance with the source connected to ground. This parameter is only visible when you select Specify from a datasheet for the Model junction capacitance parameter. The default value is 1.5 pF.

Gate-source junction capacitance

The value of the capacitance placed between the gate and the source. This parameter is only visible when you select Specify using equation parameters directly for the Model junction capacitance parameter. The default value is 3 pF.

Gate-drain junction capacitance

The value of the capacitance placed between the gate and the drain. This parameter is only visible when you select Specify using equation parameters directly for the Model junction capacitance parameter. The default value is 1.5 pF.

Ports

The block has the following ports:

G

Electrical conserving port associated with the transistor gate terminal.

D

Electrical conserving port associated with the transistor drain terminal.

S

Electrical conserving port associated with the transistor source terminal.

References

[1] H. Shichman and D. A. Hodges, Modeling and simulation of insulated-gate field-effect transistor switching circuits. IEEE J. Solid State Circuits, SC-3, 1968.

[2] G. Massobrio and P. Antognetti. Semiconductor Device Modeling with SPICE. 2nd Edition, McGraw-Hill, 1993. Chapter 2.

See Also

P-Channel JFET

  


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