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S-R Latch - Model an S-R Latch behaviorally

Library

Logic

Description

The S-R Latch block is an abstracted behavioral model of a set-reset latch. It does not model the internal individual MOSFET devices. Therefore, the block runs quickly during simulation but retains the correct I/O behavior.

The block models gate inputs electrically as having infinite resistance and a finite or zero capacitance. If the gate voltage is greater than the threshold voltage , then the input taken is 1 (HIGH). Otherwise, the input is zero (LOW). The gate threshold voltage is halfway between the Low level input voltage ( ) and High level input voltage ( ) parameters.

The block models the gate output as a voltage source driving a series resistor and a capacitor that connects to ground. The output pin connects to the resistor-capacitor connection node. The voltage source is equal to either the Low level output voltage ( ) or the High level output voltage ( ) parameter, according to the logic levels of the gate inputs and the S-R latch truth table.

S	R	Q
0	0	0
0	1	0
1	0	1
1	1	1

The block sets the value of the gate output capacitor such that the resistor-capacitor time constant is equal to the propagation delay.

Basic Assumptions and Limitations

The block does not model the internal individual MOSFET devices that make up the gate. This limitation has the following implications:

The behavior of this block is abstracted. In particular, response to input noise and inputs that are around the logic threshold voltage can be inaccurate. Also, dynamic response is approximate.
The linear drop in output voltage as a function of output current is an approximation to the MOSFET or bipolar output behavior.
Modeling of the output as a controlled voltage source is representative of a totem-pole or push-pull output stage. To model a device with an open-collector:
1. Connect the output pin to the base of an NPN Bipolar Transistor or PNP Bipolar Transistor block.
2. Set the Output resistance parameter to a suitable value.

Dialog Box and Parameters

Inputs Tab

Low level input voltage: Voltage value less than which the block interprets the input voltage as LOW. The default value is 2 V.
High level input voltage: Voltage value greater than which the block interprets the input voltage as HIGH. The default value is 3 V.
Average input capacitance: Fixed capacitance that approximates the input capacitance for a MOSFET gate. You can usually find this capacitance value on a manufacturer datasheet. The default value is 5 pF. Setting this value to zero can result in faster simulation times.

Outputs Tab

Low level output voltage: Voltage value at the output when the output logic level is LOW. The default value is 0 V.
High level output voltage: Voltage value at the output when the output logic level is HIGH. The default value is 5 V.
Output resistance: This parameter is the ratio of output voltage drop to output current. Set this parameter to , where is the reduced output high voltage when the output current is . The default value is 450 Ω.
Propagation delay: Time it takes for the output to swing from LOW to HIGH or HIGH to LOW, after the input logic levels change. The default value is 1.2e-07 s.