| SimEvents® | |
Write input signal value to memory and read memory to output signal upon events
Signal Management
The Signal Latch block is a versatile block for manipulating event-based signals. You can use it to delay or resample signals based on events, not time. This block stores and outputs the values of the in input signal based on events:
The block writes the value of the in signal to an internal memory location when a "write to memory" event occurs. The Write to memory upon parameter indicates the type of signal-based event or function call that causes a write event.
The block reads the memory value and updates the signal at the out port, if present, when a "read from memory" event occurs. The Read from memory upon parameter indicates the type of internal or external event that causes a read event:
If you set Read from memory upon to Write to memory event, then every write event causes a read event. The out signal is like a resampled version of the in signal.
Otherwise, the Read from memory upon parameter indicates the type of signal-based event or function call that causes a read event. In this case, write and read events occur independently and are not required to alternate. The out signal is like a delayed resampled version of the in signal.
This block is useful for modeling feedback loops in discrete-event systems in which an output from one component is an input to another component. Because the two components work separately in such a system, the updates of the input and output signals are independent in both causality and timing. This block lets you control the causality and timing associated with storing the output from one component and updating the value received by the other component. For an example that uses this block in a feedback loop, see the Dynamic Voltage Scaling Using Online Gradient Estimation demo.
Signal Input Ports
| Label | Description |
|---|---|
| wts | Signal whose updates cause write events. This port appears only if you set Write to memory upon to Sample time hit from port wts. |
| wtr | Trigger signal whose edges cause write events. This port appears only if you set Write to memory upon to Trigger from port wtr. |
| wvc | Signal whose numerical changes in value cause write events. This port appears only if you set Write to memory upon to Change in signal from port wvc. |
| wfcn | Function-call signal that causes write events. This port appears only if you set Write to memory upon to Function call from port wfcn. |
| rts | Signal whose updates cause read events. This port appears only if you set Read from memory upon to Sample time hit from port rts. |
| rtr | Trigger signal whose edges cause read events. This port appears only if you set Read from memory upon to Trigger from port rtr. |
| rvc | Signal whose numerical changes in value cause read events. This port appears only if you set Read from memory upon to Change in signal from port rvc. |
| rfcn | Function-call signal that causes read events. This port appears only if you set Read from memory upon to Function call from port rfcn. |
| in | Signal to be resampled and/or delayed. |
Signal Output Ports
| Label | Description | Time of Update When Statistic Is On | Order of Update | Initial Value |
|---|---|---|---|---|
| st | 0 or 1, depending on whether the block more recently processed a read or write event. | Upon write events and upon read events | 1 | 0 |
| mem | The value of the block's internal memory when a write event occurs. | Upon write events | 1 | Value of Initial memory value parameter |
| out | The value of the block's internal memory when a read event occurs. | Upon read events | 1 |
Output signals having the same number in the Order of Update column in the table above are updated in an arbitrary sequence relative to each other; you should not rely on a specific sequence for your simulation results.
The initial value is in effect from the start of the simulation until the first update by the block.
The value in the block's internal memory before the first write event occurs.
The type of signal-based event or function call that causes a write event.
Determines whether rising, falling, or either type of trigger edge causes a write event. This field appears only if you set Write to memory upon to Trigger from port wtr.
Determines whether rising, falling, or either type of value change causes a write event. This field appears only if you set Write to memory upon to Change in signal from port wvc.
Select this option to control the sequencing of the write event, relative to other simultaneous events in the simulation. If you do not select this option, the application executes the write event immediately upon detecting the signal-based event that causes it. For details, see Choosing How to Resolve Simultaneous Signal Updates.
Note If this block has a function-call input, you might need to select this option to prevent latency in the signal input. |
The priority of the write event, relative to other simultaneous events in the simulation. For details, see Specifying Event Priorities to Resolve Simultaneous Signal Updates. This field appears only if you select Resolve simultaneous signal updates according to event priority on this tab.
The type of signal-based event, function call, or internal write event that causes a read event.
Determines whether rising, falling, or either type of trigger edge causes a read event. This field appears only if you set Read from memory upon to Trigger from port rtr.
Determines whether rising, falling, or either type of value change causes a read event. This field appears only if you set Read from memory upon to Change in signal from port rvc.
Select this option to control the sequencing of the read event, relative to other simultaneous events in the simulation. If you do not select this option, the application executes the read event immediately upon detecting the signal-based event that causes it. For details, see Choosing How to Resolve Simultaneous Signal Updates. This field appears only if you set Read from memory upon to an option other than Write to memory event.
Note If this block has a function-call input, you might need to select this option to prevent latency in the signal input. |
The priority of the read event, relative to other simultaneous events in the simulation. For details, see Specifying Event Priorities to Resolve Simultaneous Signal Updates. This field appears only if you select Resolve simultaneous signal updates according to event priority on this tab.
Controls the presence of the signal output port labeled st.
Controls the presence of the signal output port labeled mem.
Controls the presence of the signal output port labeled out.
Reading from Memory Upon Each Write Event
In the plot below, the output signal reflects values of the input signal upon each rising or falling value of the wvc signal. Between successive write events, the output signal maintains the value from the most recent write event. Before the first write event, the output signal is 0 because of the initial memory value.
Independent Read and Write Events
In the plot below, the mem signal reflects values of the input signal upon each rising or falling value of the wvc signal, while the out signal reflects values of the mem signal upon each rising or falling value of the rvc signal.
For examples showing the use of this block in a model, see
Data Store Memory, Data Store Read, Data Store Write
| Set Attribute (Obsolete) | Signal Scope | |
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