Simulink® Checks

Simulink® Check Overview

Use the Simulink® Model Advisor checks to configure your model for simulation.

See Also

Check model, local libraries, and referenced models for known upgrade issues

Uses the slupdate command analysis mode to check for common upgrade issues.

Description

Check blocks, settings, and references in the model for compatibility issues resulting from using a new version of Simulink software.

Results and Recommended Actions

ConditionRecommended Action
Referenced models recommended for update.Run Simulink update tool, slupdate on the listed models.
Check library update status.Verify that indicated libraries are valid.
Check update status for the Level 2 API S-functions.Consider replacing Level 1 S-functions with Level 2.
Blocks have configuration sets or ports with undesired settings.Run Simulink update tool, slupdate in update mode.

See Also

Identify unconnected lines, input ports, and output ports

Check for unconnected lines or ports.

Description

This check lists unconnected lines or ports. These can have difficulty propagating signal attributes such as data type, sample time, and dimensions.

Results and Recommended Actions

ConditionRecommended Action
Lines, input ports, or output ports are unconnected.Ensure all signals are connected. Double-click the list of unconnected items to locate failure.

Tips

Use the PortConnectivity command to obtain an array of structures describing block input or output ports.

See Also

Common Block Parameters in the Simulink documentation for information on the PortConnectivity command.

Check root model Inport block specifications

Check that root model Inport blocks fully define dimensions, sample time, and data type.

Description

Using root model Inport blocks that do not fully define dimensions, sample time, or data type can lead to undesired simulation results. Simulink software back-propagates dimensions, sample times and data types from downstream blocks unless you explicitly assign them values.

Results and Recommended Actions

ConditionRecommended Action
Root-level Inport blocks have undefined attributes.Fully define the attributes of all root-level Inport blocks.

See Also

Check optimization settings

Unselected optimizations during code generation can lead to suboptimal results.

Description

This check lists code generation optimizations that have been turned off. Turning them on can improve code efficiency and simulation time.

Results and Recommended Actions

ConditionRecommended Action
Listed optimizations not selected.Turn on the listed optimizations in the Optimization pane Configurations Parameters dialog box.

Check for parameter tunability information ignored for referenced models

Checks if parameter tunability information is included in the Model Parameter Configuration dialog box.

Description

Simulink software ignores tunability information specified in the Model Parameter Configuration dialog box. This check identifies those models containing parameter tunability information that Simulink software will ignore if the model is referenced by other models.

Results and Recommended Actions

ConditionRecommended Action
Model contains ignored parameter tunability information.Click the links to convert to equivalent Simulink parameter objects in the MATLAB® workspace.

See Also

Parameter Storage, Interfacing, and Tuning in the Simulink documentation.

Check for implicit signal resolution

Identify models that attempt to resolve named signals and states to Simulink.Signal objects.

Description

Requiring Simulink software to resolve all named signals and states is inefficient and slows incremental code generation and model reference. This check identifies those signals and states for which you may turn off implicit signal resolution and enforce resolution.

Results and Recommended Actions

ConditionRecommended Action
Not all signals and states are resolved.Turn off implicit signal resolution and enforce resolution for each signal and state that successfully resolves.

See Also

Resolving Signal Objects for Output Data in the Simulink documentation.

Check for optimal bus virtuality

Identify virtual buses that could be made nonvirtual. Making these buses nonvirtual improves generated code efficiency.

Description

This check identifies blocks incorporating virtual buses that cross a model boundary. Changing these to nonvirtual improves generated code efficiency.

Results and Recommended Actions

ConditionRecommended Action
Blocks that specify a virtual bus crossing a model boundary.Change the highlighted bus to nonvirtual.

See Also

Check for Discrete-Time Integrator blocks with initial condition uncertainty

Identify Discrete-Time Integrator blocks with state port and initial condition ports that are fed by neither an Initial Condition nor a Constant block.

Description

Discrete-Time Integrator blocks with state port and initial condition ports might not be properly initialized unless they are fed from an Initial Condition or Constant block. This is more likely to happen when Discrete-Time Integrator blocks are used to model second-order or higher-order dynamic systems.

Results and Recommended Actions

ConditionRecommended Action
Discrete-Time Integrator blocks are not initialized during the model initialization phase.Add a Constant or Initial Condition block to feed the external Initial Condition port.

See Also

Identify disabled library links

Search model for disabled library links.

Description

Disabled library links can cause unexpected simulation results. All disabled links should be resolved before a model is saved.

Results and Recommended Actions

ConditionRecommended Action
Library links are disabled.Use Restore Link from the Link Options setting in the context menu.

Tips

See Also

The Model Browser in the Simulink documentation.

Identify parameterized library links

Search model for parameterized library links.

Description

Parameterized library links that are unintentional can result in unexpected parameter settings in your model. This can result in improper model operation.

Results and Recommended Actions

ConditionRecommended Action
Parameterized links are listed.Verify that all parameterized links are intended.

Tips

See Also

Creating Block Masks in the Simulink documentation.

Identify unresolved library links

Search the model for unresolved library links, where the specified library block cannot be found.

Description

Check for unresolved library links. Models do not simulate while there are unresolved library links.

Results and Recommended Actions

ConditionRecommended Action
Library links are unresolved.Locate missing library block or an alternative.

See Also

Fixing Unresolved Library Links

Check for proper bus usage

Identify Mux blocks used as a bus creator and any bus signal that is treated as a vector.

Description

Models should not contain bus signals that Simulink software implicitly converts to vectors. Instead, either insert a Bus to Vector conversion block between the bus signal and the block input port that it feeds, or use the Simulink.BlockDiagram.addBusToVector command.

Results and Recommended Actions

ConditionRecommended Action
Identify signals used as vectors.In the Configuration Parameters dialog box, set Mux blocks used to create bus signals to error.
Model uses buses properly.In the Configuration Parameters dialog set Bus signal treated as vector to error.
Bus signals are implicitly converted to vectors.Use Simulink.BlockDiagram.addBusToVector

or insert a Bus to Vector block.

Tips

The Bus to Vector conversion block is located in the Simulink/Signal Attributes library.

See Also

Check for potentially delayed function-call subsystem return values

Identify function-call return values that might be delayed because Simulink software inserted an implicit Signal Conversion block.

Description

To ensure that signals reside in contiguous memory, Simulink software can automatically insert an implicit Signal Conversion block in front of function-call initiator block input ports. This can result in a one-step delay in returning signal values from calling function-call subsystems. The delay can be avoided by ensuring the signal originates from a signal block within the function-call system. Or, if the delay is acceptable, insert a Unit Delay block in front of the affected input ports.

Results and Recommended Actions

ConditionRecommended Action
The listed block input ports could have an implicit Signal Conversion block.Decide if a one-step delay in returning signal values is acceptable for the listed signals.
  • If the delay is not acceptable, rework your model so that the input signal originates from within the calling subsystem.

  • If the delay is acceptable, insert a Unit Delay block in front of each listed input port.

See Also

Signal Conversion block

Unit Delay block

Identify block output signals with continuous sample time and non-floating point data type

Find continuous sample time, non-floating-point output signals.

Description

Non-floating-point signals cannot properly represent continuous variables.

Results and Recommended Actions

ConditionRecommended Action
Signals with continuous sample times have a non-floating-point data type.On the identified signals, either change the sample time to be discrete or fixed-in-minor-step ([0 1]).

See Also

Modeling and Simulating Discrete Systems in the Simulink documentation.

Check for proper Merge block usage

Analyze Merge blocks in the same tree as a group, and determine the possibility for them to execute at the same time step.

Description

Blocks that directly drive the same tree of Merge blocks should have mutually exclusive execution in each time step. This check identifies those blocks that drive the same tree of Merge blocks, and so are likely to execute at the same time step.

Input Parameters

Maximum analysis time (seconds)

Provide a maximum analysis time to execute the check.

Results and Recommended Actions

ConditionRecommended Action
Merge blocks can be interconnected to form a tree structure.Rework your model so that no blocks drive the same tree of Merge blocks.

See Also

Merge block

  


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