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Delay signal one sample period, with external Boolean reset
Additional Math & Discrete / Additional Discrete
The Unit Delay Resettable block delays a signal one sample period.
The block can reset its state based on an external reset signal R. The block has two input ports, one for the input signal u and the other for the external reset signal R. When the reset signal is false, the block outputs the input signal delayed by one time step. When the reset signal is true, the block resets the current state to the initial condition, specified by the Initial condition parameter, and outputs that state delayed by one time step.
You specify the time between samples with the Sample time parameter. A setting of -1 means the Sample time is inherited.
The Unit Delay Resettable block accepts signals of any data type supported by Simulink® software, including fixed-point data types.
Specify the initial output of the simulation.
Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specifying Sample Time in the online documentation for more information.
Direct Feedthrough | No, of the input port Yes, of the reset port |
Sample Time | Specified in the Sample time parameter |
Scalar Expansion | Yes |
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| Unit Delay External IC | Unit Delay Resettable External IC | |
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