Learn more about Simulink Design Verifier

Version 1.5 (R2009b) Simulink Design Verifier Software

This table summarizes what's new in V1.5 (R2009b):

New Features and Changes	Version Compatibility Considerations	Fixed Bugs and Known Problems	Related Documentation at Web Site
Yes Details below	Yes Summary	Bug Reports	Printable Release Notes: PDF Current product documentation

• New Functions for Verification Objectives and Constraints

• Support for Enumerated Signals and Parameters

• New Option to Stop Simulation on Proof Violation

• New sldvmakeharness Function

• New sldvreport Function

• New Support for Simulink Blocks

• Support for New Blocks

New Functions for Verification Objectives and Constraints

Use these four new functions to specify objectives and constraints within an Embedded MATLAB™ script. You can use these functions instead of the corresponding Simulink^® Design Verifier™ blocks.

Function	Purpose	Corresponding Block
sldv.assume	Proof assumption	Proof Assumption
sldv.condition	Test condition	Test Condition
sldv.prove	Proof objective	Proof Objective
sldv.test	Test objective	Test Objective

These functions:

• Identify mathematical relationships for objectives and constraints in a form that can be more natural than using block parameters

• Support specifying multiple constraints without complicating the model

• Provide access to the power of the MATLAB software

• Support separation of verification and model design

Compatibility Considerations

The following functions will be removed in a future release:

• dv.assume

• dv.condition

• dv.prove

• dv.test

To ensure models with those functions will work in future releases, replace these functions with the corresponding new function added in this release. For example, replace dv.assume with sldv.assume.

Support for Enumerated Signals and Parameters

The Simulink Design Verifier software now supports Simulink models with enumerations. All the Simulink Design Verifier library blocks support enumerated parameters, constants, and inputs.

New Option to Stop Simulation on Proof Violation

The Simulink Design Verifier software allows you to stop a model simulation if it encounters a property violation. You enable this capability by inserting a Proof Objective block into a model and setting the Stop simulation when the property is violated parameter. If the simulation detects a violation of the property specified in the Proof Objective block, it terminates with an error.

Therefore, you can now verify a counterexample that was detected during a Simulink Design Verifier analysis.

New sldvmakeharness Function

With the new sldvmakeharness function, you can:

• Create a test harness model from existing Simulink Design Verifier analysis data.

• Create an empty test harness model directly from a Simulink model.

New sldvreport Function

You can now generate and customize a report from existing Simulink Design Verifier analysis data with the new sldvreport function.

New Support for Simulink Blocks

The Simulink Design Verifier software now supports the following blocks and parameters:

• Direct Lookup Table (n-D)

• Discrete Transfer Fcn

• Lookup Table and Lookup Table (2-D) — Unless the Lookup method block parameter specifies Interpolation-Extrapolation and the block's input and output signals do not have the same floating-point data type.

• Math Function — All signal types now support the hermitian and transpose function parameter settings

• Rate Limiter — For signals of all data types

• Shift Arithmetic — For all parameters and signals of all data types

• Tapped Delay

• Transfer Fcn Direct Form II

• Transfer Fcn Direct Form II Time Varying

Support for New Blocks

The Simulink Design Verifier software supports the following new Simulink blocks:

• Discrete PID Controller

• Discrete PID Controller (2 DOF)

• Enumerated Constant

Simulink Design Verifier Release Notes

Version 1.4 (R2009a) Simulink Design Verifier Software

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