Learn more about Simulink Design Verifier

Version 1.3 (R2008b) Simulink Design Verifier Software

This table summarizes what's new in V1.3 (R2008b):

New Features and Changes	Version Compatibility Considerations	Fixed Bugs and Known Problems	Related Documentation at Web Site
Yes Details below	Yes Summary	Bug Reports	Printable Release Notes: PDF Current product documentation

New features and changes introduced in this version are:

• Simulink Bus Signals and Bus Objects Support

• Fixed-Point Data Support

• Generating Test Harness Model with Model Reference

• Generating SystemTest TEST-File

• Improved Search Algorithms

• New Data File Format

• New HTML Report

• Blocks with No Input Ports Limitation

Simulink Bus Signals and Bus Objects Support

Simulink Design Verifier now supports Simulink buses and bus objects:

• The root Inport and Outport blocks accept bus signals.

• Nonvirtual buses are propagated through the model elements.

• The test harness model reconstructs the needed bus signals from the underlying bus elements.

Fixed-Point Data Support

Simulink Design Verifier blocks now support fixed-point parameters and inputs. These blocks include:

• Test Condition

• Test Objective

• Assumption

• Proof Objective

The Slvd.Point and Sldv.Interval constructors now accept fixed-point data.

Generating Test Harness Model with Model Reference

To use this option, select Reference input model in generated harness in the Design Verifier > Results pane of the Configuration Parameters dialog box. Simulink Design Verifier software then uses model reference to run the original model from the test harness.

Generating SystemTest TEST-File

To use this option, select Save test harness as SystemTest TEST-File in the Design Verifier > Results pane of the Configuration Parameters dialog box. The software creates a TEST-file instead of a test harness model. Using a TEST-file allows you to run the test cases in the SystemTest™ environment and configure the model coverage settings using the SystemTest software.

Improved Search Algorithms

This release includes search algorithms for the following two modes that improve the performance and the quality of the results:

• Test case generation — The combined objectives options minimizes the number of test cases by generating cases that address more than one test objective.

• Property proving — Proving that model properties are valid.

New Data File Format

When the Simulink Design Verifier software completes an analysis, it creates a data file. Now the data file supports bus input ports and includes more information about the analyzed model. For more information, see Examining Simulink Design Verifier Data Files in the Simulink Design Verifier documentation.

Compatibility Considerations

To convert an sldvData structure from the old format to the new format, use the Sldv.DataUtils.convertToCurrentFormat utility with the following syntax:

new_sldvData = Sldv.DataUtils.convertToCurrentFormat(model, old_sldvData)

The arguments used for this conversion comprise:

• model — The name of the model that was analyzed

• old_sldvData — The name of an sldvData structure created using the old (pre-R2008b) format

To convert an sldvData structure in the new format to the old format, use the Sldv.DataUtils.convertToOldFormat utility with the following syntax:

old_sldvData = Sldv.DataUtils.convertToOldFormat(model, new_sldvData)

The arguments used for this conversion comprise:

• model — The name of the model that was analyzed

• new_sldvData — The name of an sldvData structure created using the format that is new with R2008b

New HTML Report

The HTML report that Simulink Design Verifier software generates has been enhanced. Now, when you select Generate report of the results in the Design Verifier > Report pane of the Configuration Parameters dialog box, the report generated has several improvements:

• The report generates faster and is easier to understand.

• The report can display expected outputs.

• The software generates a report that reflect the analysis settings (for example, test case generation vs. property proving).

Blocks with No Input Ports Limitation

If a Simulink model has any blocks with no input ports, Simulink Design Verifier software cannot generate the test harness.

Version 1.4 (R2009a) Simulink Design Verifier Software

Version 1.2 (R2008a) Simulink Design Verifier Software

© 1984-2009- The MathWorks, Inc.    -   Site Help   -   Patents   -   Trademarks   -   Privacy Policy   -   Preventing Piracy   -   RSS