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Version 1.4 (R2009a) Simulink Design Verifier Software

This table summarizes what's new in V1.4 (R2009a):

New Features and ChangesVersion Compatibility ConsiderationsFixed Bugs and Known ProblemsRelated Documentation at Web Site
Yes
Details below
NoBug Reports

Printable Release Notes: PDF

Current product documentation

New features and changes introduced in this version are:

Automatic Stubbing for Unsupported Operations

Automatic stubbing allows you to complete a test-generation or property-proving analysis even if the model contains blocks or functions that the Simulink Design Verifier software does not support, like S-functions and C math operations.

By default, this feature is unavailable. To enable automatic stubbing before running an analysis, on the Configuration Parameters Design Verifier main pane, select Automatic stubbing of unsupported blocks and functions. In addition, if the compatibility check finds unsupported blocks that automatic stubbing can handle, you can enable automatic stubbing at that time.

Long Test Case Optimization

Long test cases is a new option for the Test suite optimization parameter. The Long test cases option instructs the Simulink Design Verifier software to create fewer but longer test cases that each satisfy multiple test objectives. With this option, you can customize the analysis results, run a more efficient analysis, and create easier-to-review results, in both Signal Builder and in the HTML report that the software generates.

New Support for Blocks

The Simulink Design Verifier software now supports models containing the following blocks:

Analyzing External M-Files for Embedded MATLAB Function Blocks

If your model contains an Embedded MATLAB Function block that calls any external M-files, the Simulink Design Verifier software can now accumulate coverage results for those M-files.

Enhanced Block Replacement Capability for Subsystems and Model Blocks

You can write your own replacement rules to replace subsystem or Model blocks that reference another model with theSimulink Design Verifier block replacement capability. The software replaces a subsystem or Model block with a different subsystem or with a built-in block as defined in the block replacement rules.

New Implies Block

The new Implies block simplifies property specification. You can now specify conditions that produce a given response. For example, you can quickly create expressions indicating that pressing the break pedal implies the cruise control must be inactive.

You can use the Implies block in any model, not just when running the Simulink Design Verifier software.

New Property-Proving Examples and Demos

The Simulink Design Verifier block library includes four new example models that demonstrate how to define complex properties for property-proving analysis.

In addition, the following demo models are shipping with R2009a:

sldvisactive Function

The sldvisactive function checks whether the Simulink Design Verifier software is actively translating the model. This function is called from the masked initialization of masked subsystems and other model or block callbacks to configure the model, as needed, for Simulink Design Verifier analysis.

For example, the mask initialization of the Environment Controller block invokes the sldvisactive function to output the signal at its Sim port when you start analyzing a model that contains the block.

  


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