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Unsupported Simulink Software Features

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Simulink Software Features Not Supported Simulink Block Support Limitations Limitations of Support for Model Reference

Simulink Software Features Not Supported

The Simulink Design Verifier software does not support the following Simulink software features. Avoid using these unsupported features in models that you analyze with the Simulink Design Verifier software.

Not Supported	Description
Variable-step solvers	The Simulink Design Verifier software supports only fixed-step solvers. (See Choosing a Fixed-Step Solver.)
Callback functions	The Simulink Design Verifier software does not execute model callback functions during the analysis. As a result, if a callback function changes any model parameters or workspace variables, the analysis does not reflect those changes. Callbacks called prior to analysis, such as the PreLoadFcn or PostLoadFcn model callbacks, are fully supported.
Complex signals	The Simulink Design Verifier software supports only real signals. (For contrast, see Complex Signals in Simulink User's Guide.)
Variable-size signals	The Simulink Design Verifier software does not support variable-size signals. A variable-size signal is a signal whose size (number of elements in a dimension), in addition to its values, can change during model execution. For more information, see Working with Variable-Size Signals in Simulink User's Guide.
Multiword fixed-point data types	The Simulink Design Verifier software does not support multiword fixed-point data types.
Signals with nonzero sample time offset	The Simulink Design Verifier software does not support models with signals that have nonzero sample time offsets.
Nonzero start times	Although Simulink allows you to specify a nonzero simulation start time, the Simulink Design Verifier software generates signal data that begins only at zero. If your model specifies a nonzero start time: If you do not select the Reference input model in generated harness parameter (the default), the harness model is a subsystem. The software sets the start time of the harness model to 1 and continues the analysis. If you select the Reference input model in generated harness parameter, a Model block references the harness model. The Simulink Design Verifier software cannot change the start time of the harness model, so the analysis stops and you see a recommendation to set the Start time parameter to 0.

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Simulink Block Support Limitations

The Simulink Design Verifier software provides various levels of support for Simulink blocks. The software either fully or partially supports particular blocks. It does not support other blocks.

If your model contains unsupported blocks, you can turn on automatic stubbing, which considers the interface of the unsupported blocks, but not their behavior. However, if any of the unsupported blocks affect the simulation outcome, the analysis may achieve only partial results. For details about automatic stubbing, see Handling Incompatibilities with Automatic Stubbing.

To guarantee 100% coverage, avoid using unsupported blocks in models that you analyze with the Simulink Design Verifier software.

Similarly, specify only the block parameters that the Simulink Design Verifier software recognizes for blocks that it partially supports. See Simulink Block Support.

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Limitations of Support for Model Reference

The Simulink Design Verifier software supports the Model block, but with the following limitations. The software cannot analyze a model that contains one or more Model blocks if:

• Simulink Design Verifier software does not support protected referenced models. Protected referenced models are encoded to obscure their contents. This feature allows third parties to use the referenced model without being able to view the intellectual property that makes up the model. For more information, see Protecting Referenced Models in the Simulink User's Guide.

• The parent model or any of the referenced models gives an error when one of the following model parameters is set to Error:

  • Diagnostics > Connectivity > Element name mismatch

  • Diagnostics > Connectivity > Mux blocks used to create bus signals

  You can use the Element name mismatch diagnostic along with bus objects to ensure that your model meets bus element naming requirements imposed by some blocks.

  If your model contains Mux blocks that create bus signals, refer to "Tips" in Mux blocks used to create bus signals to resolve this problem.

• A referenced model references a variable in its workspace that is either defined in its own workspace or in the base MATLAB workspace, and it is also defined with the same name in the parent model's workspace. Rename the variable used by the referenced model to a unique name so that you can analyze the model.

  Exception: If the parent model and a referenced model both define an instance of a Simulink.Signal object used as local data storage with the same name, the software can analyze the model.

• Any of the models in the model reference hierarchy have algebraic loops that cannot be eliminated with algebraic loop minimization. If you encounter this limitation, set the Minimize algebraic loop parameter on the Diagnostics pane of the Configuration Parameters dialog box to Error. Then, update the model to identify the location of algebraic loop in the model.

  To eliminate this problem so that the software can analyze the model, break any algebraic loops with Unit Delay blocks to ensure that the execution order is predictable.

  For more information, see Algebraic Loops in the Simulink User's Guide.

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Checking Model Compatibility

Unsupported Stateflow Software Features

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