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The Simulink Design Verifier software does not support calls to MATLAB functions or access to MATLAB workspace variables, which the Stateflow software allows (see Using MATLAB Functions and Data in Actions in the Stateflow and Stateflow Coder User's Guide) .

C math functions

The Simulink Design Verifier software supports calls to the following C math functions: abs, ceil, fabs, floor, fmod, labs, ldexp, and pow (only for an integer exponent).

The software does not support calls to other C math functions that the Stateflow software allows. Turning on automatic stubbing allows these functions to be eliminated during the analysis. For details about automatic stubbing, see Handling Incompatibilities with Automatic Stubbing.

For information about C math functions in Stateflow, see Calling C Functions in Actions in the Stateflow and Stateflow Coder User's Guide)

Recursion

The Simulink Design Verifier software does not support recursive functions, which the Stateflow software allows you to implement using graphical functions (see Using Graphical Functions to Extend Actions in the Stateflow and Stateflow Coder User's Guide) . Also, the Simulink Design Verifier software does not support recursion that the Stateflow software allows you to implement using a combination of event broadcasts and function calls.

Custom C or C++ code

The Simulink Design Verifier software does not support custom C or C++ code, which the Stateflow software allows (see Building Targets in the Stateflow and Stateflow Coder User's Guide) .

Textual functions with literal string arguments

The Simulink Design Verifier software does not support literal string arguments to textual functions in a Stateflow chart.

Machine-parented data and events

The Simulink Design Verifier software does not support machine-parented data and events (i.e., defined at the level of the Stateflow machine in the Stateflow hierarchy), which the Stateflow software allows (see Defining Data and Defining Events in the Stateflow and Stateflow Coder User's Guide) .

Absolute-time temporal logic

The Simulink Design Verifier software does not support absolute-time temporal logic, which the Stateflow software allows (see Operators for Absolute-Time Temporal Logic in the Stateflow and Stateflow Coder User's Guide) .