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| Documentation → Simulink Design Verifier |
| Contents | Index |
| Learn more about Simulink Design Verifier |
| On this page… |
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Constructing the Example Model Checking Compatibility of the Example Model |
The sections that follow describe a Simulink model for which you generate test cases that achieve decision coverage. This example demonstrates the test-generation capabilities of the Simulink Design Verifier software.
The following workflow guides you through the process of completing this example.
| Task | Description | See... |
|---|---|---|
| 1 | Construct the example model. | |
| 2 | Ensure your model's compatibility with the Simulink Design Verifier software. | |
| 3 | Configure the Simulink Design Verifier software to generate tests. | |
| 4 | Generate test cases for your model and interpret the results. | |
| 5 | Add a Test Condition block to customize test generation. | |
| 6 | Generate test cases for your modified model and interpret the results. |
In this task, you construct a Simulink model that you use throughout the remaining tasks:
Create a new Simulink model.
Copy the following blocks into your empty model window:
From the Sources library, an Inport block to initiate the input signal whose value the Simulink Design Verifier software controls
From the Signal Routing library, a Switch block to provide simple logic
From the Sources library, two Constant blocks to serve as Switch block data inputs
From the Sinks library, an Outport block to receive the output signal
In your model, double-click one of the Constant blocks and specify its Constant value parameter as 2.
Connect the blocks so that your model appears similar to the following diagram.
Save your model as example.mdl for use in the remaining tasks.
In this task, you ensure that your model is compatible for use with the Simulink Design Verifier software. Specifically, you check the compatibility of the example model:
In your Simulink model window, select Tools > Design Verifier > Check Model Compatibility.
The Simulink Design Verifier software displays the following log window, which indicates that your model is incompatible.
It also displays in the Simulation Diagnostics Viewer the following incompatibility error.
The error message informs you that the Simulink Design Verifier software does not support variable-step solvers. To work around this incompatibility, use a fixed-step solver.
In your Simulink model window, select Simulation > Configuration Parameters to open the Configuration Parameters dialog box.
On the left side of the Configuration Parameters dialog box, in the Select tree, click the Solver category (if not already selected). Under Solver options on the right side, set the Type option to Fixed-step and set the Solver option to Discrete (no continuous states).
Click Apply and then OK to apply your changes and close the Configuration Parameters dialog box.
Verify the compatibility of your model. In your Simulink model window, select Tools > Design Verifier > Check Model Compatibility.
The Simulink Design Verifier software displays the following log window, which confirms that your model is compatible for analysis.
Save your model for use in the next task.
If the compatibility check indicates that your model is partially compatible, your model contains at least one element that is incompatible with the Simulink Design Verifier software. You can continue analyzing a partially compatible model if you turn on automatic stubbing. For details, see Handling Incompatibilities with Automatic Stubbing.
In this task, you configure the Simulink Design Verifier software to generate test cases that achieve complete decision coverage for your simple model:
In your Simulink model window, select Tools > Design Verifier > Options.
In the Configuration Parameters dialog box, you see the Simulink Design Verifier options.
On the left side of the Configuration Parameters dialog box, in the Select tree, click the Design Verifier category (if not already selected). Under Analysis options on the right side, ensure that the Mode option specifies Test generation.
On the left side of the Configuration Parameters dialog box, in the Select tree, click the Test Generation category.
On the Test Generation pane, set the value of the Model coverage objectives parameter to Decision.
Click Apply and then OK to apply your change and close the Configuration Parameters dialog box.
Save your model for use in the next task.
Note On the Test Generation pane, you can optionally specify values for other parameters that control how the Simulink Design Verifier software generates test cases for your model. For more information, see Test Generation Pane. |
In this task, you execute the Simulink Design Verifier analysis that you configured in the previous task. The software generates test cases for your example model and produces results for you to interpret:
In your model window, select Tools > Design Verifier > Generate Tests.
The Simulink Design Verifier software begins analyzing your model to generate test cases. During its analysis, the software displays a log window.
In the Simulink Design Verifier log window, you can see how the proof progresses. You see information such as the number of test objectives processed and how many of those objectives were satisfied. Also in this dialog box, you can click Stop to terminate the proof at any time.
When the software completes its analysis, it displays the following items:
An HTML report named example_report.html
A test harness model named example_harness.mdl
A Signal Builder window containing the test-case signals
The remaining steps in this section help you to interpret the results.
Review the Simulink Design Verifier report, starting with the Table of Contents. Click an item to navigate in the report.
In the Table of Contents, click Summary to display the report's Summary chapter.
The Summary chapter lists information about the model and the status of the objectives—satisfied or not.
In the Table of Contents, click Analysis Information to display the Analysis Information chapter.
The Analysis Information chapter provides information about:
The model you analyzed
The options you specified for the analysis
Approximations the software performed during the analysis
In the Table of Contents, click Test Objectives Status to display the report's Test Objectives Status chapter.
This table indicates that the software satisfied both test objectives associated with the Switch block in your model, for which it generated two test cases.
Under the table Test Case column, click 2 to display the Test Case 2 section.
This section provides details about a test case that the Simulink Design Verifier software generated to achieve an objective in your model. This test case achieves test objective 1, which involves the Switch block passing its third input. Specifically, the software determined that a value of –1 for the Switch block control signal enables the block to pass its third input.
Review the harness model named example_harness.mdl.
The harness model contains the following items:
Signal Builder block named Inputs — Groups of signals that achieve test objectives in your model
Subsystem block named Test Unit — A copy of your model
DocBlock named Test Case Explanation — A text description of the test cases that the Simulink Design Verifier software generates
Note For more information about interacting with blocks such as the Signal Builder, Subsystem, and DocBlock, see the Simulink Reference. |
To simulate the test harness and confirm that the test cases achieve complete decision coverage, double-click the Inputs block to open the Signal Builder dialog box.
In the Signal Builder dialog box, click the Run
all button
.
The Simulink Design Verifier software simulates the test harness using all the test cases, collects model coverage information, and displays a coverage report that includes the following Summary.
The coverage report indicates that the software generated test cases that achieve complete decision coverage for your example model (see Model Coverage Reports in the Simulink Verification and Validation User's Guide).
If you prefer to review results that are combined into a smaller number of longer test cases, set the Test suite optimization parameter to Long test cases and rerun the analysis. In the Long test cases optimization, the analysis generates fewer but longer test cases that each satisfy multiple test objectives. This optimization creates a more efficient analysis and easier-to-review results.
To compare the Long test cases results to the Combined objectives results (the default), see Combining Test Cases.
In this task, you modify the example model for which you attained complete decision coverage. Specifically, you customize test generation by adding and configuring a Test Condition block:
In the MATLAB Command Window, enter sldvlib to display the Simulink Design Verifier library.
Copy the Test Condition block to your model by dragging it from the Simulink Design Verifier library to your model window.
In the model window, insert the Test Condition block between the Switch and Outport blocks.
In your model, double-click the Test Condition block to access its attributes.
The Test Condition block parameter dialog box opens.
In the Values box, enter [-0.1, 0.1]. When generating test cases for this model, the Simulink Design Verifier software constrains the signal values, entering the Switch block control port to the specified interval.
Click Apply then OK to apply your changes and close the Test Condition block parameter dialog box.
Save your model for use in the next task.
Simulink Design Verifier blocks are preserved with a model, even if you open the model on a MATLAB installation that does not have a Simulink Design Verifier license. If you then open the model on a system with a Simulink Design Verifier license, the software can analyze the model with the blocks and options that you originally added to the model.
In this task, you analyze the example model with the Test Condition block. To observe how the Test Condition block affects test generation, compare the result of this analysis to the result that you obtained in Analyzing the Example Model.
In the model window, select Tools > Design Verifier > Generate Tests.
The Simulink Design Verifier software displays a log window and begins analyzing your model to generate test cases.
When the software completes the analysis, it displays a new Simulink Design Verifier report named example_report1.html.
To begin reviewing the report, in the Table of Contents, click Summary.
The Summary chapter indicates that the Simulink Design Verifier software satisfied two test objectives in your model.
In the Table of Contents, click Analysis Information. Scroll to the bottom of this chapter, to the Constraints section.
This section lists the Test Condition block that you added to constrain the value of the Switch block control signal to the interval [–0.1, 0.1].
In the Table of Contents, click Test Objectives Status.
This table indicates that the Simulink Design Verifier software satisfied both test objectives associated with the Switch block in your model, for which it generated two test cases.
Under the table Test Cases column, click 2.
This section provides details about a test case that the software generated to achieve an objective in your model. This test case achieves test objective 1, which involves the Switch block passing its third input. Although the Test Condition block restricts the domain of input signals to the interval [–0.1, 0.1], the software determines that a value of –0.05 for the Switch block control signal satisfies the objective.
To confirm that the test case achieves complete decision coverage, go to the harness model named example_harness1.mdl.
Double-click the Inputs block to open the Signal Builder dialog box.
In the Signal Builder dialog box, click the Run
all button
.
The Simulink software simulates the test harness using both test cases, collects model coverage information, and displays a coverage report whose Summary section appears as follows.
The coverage report indicates that the Simulink Design Verifier software generated test cases that achieve complete decision coverage for your example model.
If the analysis produces the error The model is contradictory in its current configuration, the software detected a contradiction in your model and cannot analyze the model. You have a contradiction if your model has Test Objective blocks with incorrect parameters. For example, an objective that states that a signal must be between 0 and 5 when the signal is constant 10.
If the software detects a contradiction, all previous results are invalidated and the software reports that the some of the objectives cannot be satisfied.
 | Workflow for Generating Test Cases | Generating Test Cases for a Subsystem |  |
Learn more about Simulink through this collection of videos, articles, technical literature and the Getting Started with Simulink Guide.
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