Learn more about Simulink Design Verifier

Test Objective - Define custom objectives that signals must satisfy in test cases

Library

Simulink Design Verifier

Description

When operating in test generation mode, the Simulink Design Verifier software produces test cases that satisfy specified criteria (see Generating Test Cases). In this mode, you can use Test Objective blocks to define custom test objectives for signals in your model. The Values parameter lets you specify values that a signal must achieve for at least one time step during a test case simulation. The block applies the specified Values parameter to its input signal, and the Simulink Design Verifier software attempts to produce test cases that satisfy the objective.

The block's parameter dialog box also allows you to

Enable or disable the objective.
Specify that the block should display its Values parameter in the model editor.
Specify that the block should display its output port.

Note The Simulink and Real-Time Workshop software ignore the Test Objective block during model simulation and code generation, respectively. The Simulink Design Verifier software uses the Test Objective block only when generating test cases for a model.

Specifying Test Objectives

Use the Values parameter to define custom objectives that signals must satisfy in test cases. Specify any combination of scalars and intervals in the form of a MATLAB cell array. (For information about cell arrays, see Cell Arrays in the MATLAB documentation.)

Tip If the Values parameter specifies only one scalar value, you do not need to enter it in the form of a MATLAB cell array.

Scalar values each comprise a single cell in the array, for example:

{0, 5}

A closed interval comprises a two-element vector as a cell in the array, where each element specifies an interval endpoint:

{[1, 2]}

Alternatively, you can specify scalar values using the Sldv.Point constructor, which accepts a single value as its argument. You can specify intervals using the Sldv.Interval constructor, which requires two input arguments, i.e., a lower bound and an upper bound for the interval. Optionally, you can provide one of the following strings as a third input argument that specifies inclusion or exclusion of the interval endpoints:

'()' — Defines an open interval.
'[]' — Defines a closed interval.
'(]' — Defines a left-open interval.
'[)' — Defines a right-open interval.

Note By default, Sldv.Interval considers an interval to be closed if you omit its third input argument.

As an example, the Values parameter

{0, [1, 3]}

specifies:

0 — a scalar
[1, 3] — a closed interval

The Values parameter

{Sldv.Interval(0, 1, '[)'), Sldv.Point(1)}

specifies:

Sldv.Interval(0, 1, '[)') — the right-open interval [0, 1)
Sldv.Point(1) — a scalar

Data Type Support

The Test Objective block accepts signals of all built-in data types supported by the Simulink software. For a discussion on the data types supported by the Simulink software, see Data Types Supported by Simulink in Simulink User's Guide.

Parameters and Dialog Box

Enable: Specify whether the block is enabled. If selected (the default), the Simulink Design Verifier software uses the block when generating tests for a model. Clearing this option disables the block, that is, causes the Simulink Design Verifier software to behave as if the Test Objective block did not exist. If this option is not selected, the block appears grayed out in the model editor.
Type: Specify whether the block behaves as a Test Objective or Proof Objective block. Select Proof Objective to transform the Test Objective block into a Proof Objective block.
Values: Specify the test objective (see Specifying Test Objectives).
Display values: Specify whether the block displays the contents of its Values parameter in the model editor. By default, this option is selected.
Pass through style: Specify whether the block displays an output port in the model editor. If selected (the default), the block displays its output port, allowing its input signal to pass through as the block output. If not selected, the block hides its output port and terminates the input signal. The following figure illustrates the appearance of the block in each case.