Overview

  Creating a Folder and Local Model File

  Initializing Model Parameters with hdlsetup

  Generating a VHDL Entity from a Subsystem

  Generating VHDL Test Bench Code

  Verifying Generated Code

  Generating a Verilog Module and Test Bench

  Simulink HDL Coder GUI Overview

  Creating a Folder and Local Model File

  Viewing Coder Options in the Configuration Parameters Dialog Box

  Creating a Control File

  Initializing Model Parameters with hdlsetup

  Selecting and Checking a Subsystem for HDL Compatibility

  Generating VHDL Code

  Generating VHDL Test Bench Code

  Verifying Generated Code

  Generating Verilog Model and Test Bench Code

  HDL Coder Options in the Configuration Parameters Dialog Box

  HDL Coder Options in the Model Explorer

  HDL Coder Menu

  HDL Coder Top-Level Pane Overview

  File name

  Generate HDL for

  Language

  Directory

  Code Generation Output

  Generate traceability report

  Include requirements in block comments

  Global Settings Overview

  Reset type

  Reset asserted level

  Clock input port

  Clock enable input port

  Oversampling factor

  Reset input port

  Comment in header

  Verilog file extension

  VHDL file extension

  Entity conflict postfix

  Package postfix

  Reserved word postfix

  Split entity and architecture

  Split entity file postfix

  Split arch file postfix

  Clocked process postfix

  Enable prefix

  Pipeline postfix

  Complex real part postfix

  Complex imaginary part postfix

  Input data type

  Output data type

  Clock enable output port

  Represent constant values by aggregates

  Use "rising_edge" for registers

  Loop unrolling

  Cast before sum

  Use Verilog `timescale directives

  Inline VHDL configuration

  Concatenate type safe zeros

  Optimize timing controller

  Test Bench Overview

  HDL test bench

  Cosimulation blocks

  Cosimulation model for use with:

  Test bench name postfix

  Force clock

  Clock high time (ns)

  Clock low time (ns)

  Hold time (ns)

  Setup time (ns)

  Force clock enable

  Clock enable delay (in clock cycles)

  Force reset

  Reset length (in clock cycles)

  Hold input data between samples

  Initialize test bench inputs

  Multi-file test bench

  Test bench reference postfix

  Test bench data file name postfix

  Ignore output data checking (number of samples)

  EDA Tool Scripts Overview

  Generate EDA scripts

  Generate multicycle path information

  Compile file postfix

  Compile Initialization

  Compile command for VHDL

  Compile command for Verilog

  Compile termination

  Simulation file postfix

  Simulation initialization

  Simulation command

  Simulation waveform viewing command

  Simulation termination

  Synthesis file postfix

  Synthesis initialization

  Synthesis command

  Synthesis termination

  Overview

  Configuring Model Parameters

  Configuring Sample Rates in the Model

  Constraints for Rate Transition Blocks and Other Blocks in Multirate Models

  Why Use a Global Oversampling Clock?

  Requirements for the Oversampling Factor

  Specifying the Oversampling Factor From the GUI

  Specifying the Oversampling Factor From the Command Line

  Resolving Oversampling Rate Conflicts

  Overview

  Format and Content of a Multicycle Path Information File

  File Naming and Location Conventions

  Generating Multicycle Path Information Files Using the GUI

  Generating Multicycle Path Information Files Using the Command Line

  Limitations

  Demo

  Overview

  HoldInputDataBetweenSamples

  OptimizeTimingController

  What Is a Control File?

  Selectable Block Implementations and Implementation Parameters

  Implementation Mappings

  Control File Demo

  Overview

  hdlnewcontrol

  forEach

  forAll

  set

  generateHDLFor

  hdlnewcontrolfile

  Where to Locate Your Control Files

  Creating a Control File and Saving Your HDL Code Generation Settings

  Making Your Control Files More Portable

  Associating an Existing Control File with Your Model

  Detaching a Control File from Your Model

  Setting Up HDL Code Generation Defaults with a Control File

  Overview

  Generating Selection/Action Statements with the hdlnewforeach Function

  Overview

  Implementations for Commonly Used Blocks

  Math Function Block Implementations

  Divide Block Implementations

  Subsystem Interfaces and Special-Purpose Implementations

  A Note on Cascade Implementations

  Block Usage, Requirements, and Restrictions

  Restrictions on Use of Blocks in the Test Bench

  Overview

  CoeffMultipliers

  Distributed Arithmetic Implementation Parameters for Digital Filter Blocks

  InputPipeline

  OutputPipeline

  ResetType

  Interface Generation Parameters

  Complex Coefficients and Data Support for the Digital Filter and Biquad Filter Blocks

  Lookup Table (n-D)

  Prelookup

  Direct Lookup Table (n-D)

  Lookup Table

  Overview of RAM Blocks

  Dual Port RAM Block

  Simple Dual Port RAM Block

  Single Port RAM Block

  Code Generation with RAM Blocks

  Limitations for RAM Blocks

  Generic RAM and ROM Demos

  Overview

  Counter Modes

  Control Ports

  Defining the Counter Data Type and Size

  HDL Implementation and Implementation Parameters

  Parameters and Dialog Box

  Overview

  Block Inputs and Outputs

  HDL Implementation and Implementation Parameters

  Parameters and Dialog Box

  Overview

  HDL Streaming FFT Block Demo

  Block Inputs and Outputs

  Timing Description

  HDL Implementation and Implementation Parameters

  Parameters and Dialog Box

  Overview of Bitwise Operator Blocks

  Bit Concat

  Bit Reduce

  Bit Rotate

  Bit Shift

  Bit Slice

  Defaults for Model Generation

  GUI Options

  Generated Model Properties for makehdl

  Fixed-Point Limitation

  Double-Precision Limitation

  Traceability and the Code Generation Report

  Generating an HTML Code Generation Report from the GUI

  Generating an HTML Code Generation Report from the Command Line

  Keeping the Report Current

  Tracing from Code to Model

  Tracing from Model to Code

  Mapping Model Elements to Code Using the Traceability Report

  HTML Code Generation Report Limitations

  Simulink Annotations

  Text Comments

  Requirements Comments and Hyperlinks

  Removing the HDL Coder Configuration Component From a Model

  Adding the HDL Coder Configuration Component To a Model

  Generating Black Box Control Statements Using hdlnewblackbox

  Code Generation for Enabled Subsystems

  Code Generation for Triggered Subsystems

  Best Practices for Using Enabled and Triggered Subsystems

  Overview

  Generating a Cosimulation Model from the GUI

  Structure of the Generated Model

  Launching a Cosimulation

  The Cosimulation Script File

  Complex and Vector Signals in the Generated Cosimulation Model

  Generating a Cosimulation Model from the Command Line

  Naming Conventions for Generated Cosimulation Models and Scripts

  Limitations for Cosimulation Model Generation

  Overview

  Demos and Related Documentation

  Overview

  Location of Charts in the Model

  Data Type Usage

  Chart Initialization

  Registered Output

  Restrictions on Imported Code

  Using Input and Output Events

  Other Restrictions

  Software Realization of Chart Semantics

  Hardware Realization of Stateflow Semantics

  Restrictions for HDL Realization

  Overview

  Generating HDL for a Mealy Finite State Machine

  Generating HDL Code for a Moore Finite State Machine

  Temporal Logic

  Graphical Function

  Hierarchy and Parallelism

  Stateless Charts

  Truth Tables

  HDL Applications for the Embedded MATLAB Function Block

  Related Documentation and Demos

  Example Model Overview

  Setting Up

  Creating the Model and Configuring General Model Settings

  Adding an Embedded MATLAB Function Block to the Model

  Setting Optimal Fixed-Point Options for the Embedded MATLAB Function Block

  Programming the Embedded MATLAB Function Block

  Constructing and Connecting the DUT_eML_Block Subsystem

  Compiling the Model and Displaying Port Data Types

  Simulating the eml_hdl_incrementer_tut Model

  Generating HDL Code

  The eml_hdl_design_patterns Library

  Efficient Fixed-Point Algorithms

  Using Persistent Variables to Model State

  Creating Intellectual Property with the Embedded MATLAB Function Block

  Modeling Control Logic and Simple Finite State Machines

  Modeling Counters

  Modeling Hardware Elements

  Overview

  Bitwise Functions Supported for HDL Code Generation

  Bit Slice and Bit Concatenation Functions

  Shift and Rotate Functions

  Introduction

  Declaring Complex Signals

  Conversion Between Complex and Real Signals

  Arithmetic Operations on Complex Numbers

  Support for Vectors of Complex Numbers

  Other Operations on Complex Numbers

  Overview

  Example: Multiplier Chain

  Limitations

  Introduction

  Use Compiled External M-Functions on the Embedded MATLAB Path

  Build the Embedded MATLAB Code First

  Use the hdlfimath Utility for Optimized FIMATH Settings

  Use Optimal Fixed-Point Option Settings

  Fixed-Point Runtime Library Support

  Variables and Constants

  Use of Nontunable Parameter Arguments

  Arithmetic Operators

  Relational Operators

  Logical Operators

  Control Flow Statements

  Overview

  Structure of Generated Script Files

  Properties for Controlling Script Generation

  Controlling Script Generation with the EDA Tool Scripts GUI Pane