Overview of Exercises

The coder supports HDL code generation in your choice of environments:

• The MATLAB Command Window supports code generation using the makehdl, makehdltb, and other functions.

• The Simulink GUI (the Configuration Parameters dialog box and/or Model Explorer) provides an integrated view of the model simulation parameters and HDL code generation parameters and functions.

The hands-on exercises in this chapter introduce you to the mechanics of generating and simulating HDL code, using the same model to generate code in both environments. In a series of steps, you will

• Configure a simple model for code generation.

• Generate VHDL code from a subsystem of the model.

• Generate a VHDL test bench and scripts for the Mentor Graphics ModelSim simulator to drive a simulation of the model.

• Compile and execute the model and test bench code in the simulator.

• Generate and simulate Verilog code from the same model.

• Check a model for compatibility with the coder.

Before You Generate Code

The sfir_fixed Demo Model

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