Properties — Alphabetical List

By Category

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BlockGenerateLabel
CastBeforeSum
CheckHDL
ClockEnableInputPort
ClockEnableOutputPort
ClockHighTime
ClockInputPort
ClockLowTime
ClockProcessPostfix
CodeGenerationOutput
ComplexImagPostfix
ComplexRealPostfix
EDAScriptGeneration
EnablePrefix
EntityConflictPostfix
ForceClock
ForceClockEnable
ForceReset
GenerateCoSimBlock
GenerateCoSimModel
Generatedmodelname
Generatedmodelnameprefix
HDLCompileInit
HDLCompileTerm
HDLCompileFilePostfix
HDLCompileVerilogCmd
HDLCompileVHDLCmd
HDLControlFiles
HDLMapPostfix
HDLSimCmd
HDLSimInit
HDLSimFilePostfix
HDLSimTerm
HDLSimViewWaveCmd
HDLSynthCmd
HDLSynthInit
HDLSynthFilePostfix
HDLSynthTerm
Highlightancestors
Highlightcolor
HoldInputDataBetweenSamples
HoldTime
IgnoreDataChecking
InitializeTestBenchInputs
InlineConfigurations
InputType
InstanceGenerateLabel
InstancePrefix
LoopUnrolling
MulticyclePathInfo
MultifileTestBench
OptimizeTimingController
OutputGenerateLabel
OutputType
Oversampling
PackagePostfix
PipelinePostfix
RequirementComments
ReservedWordPostfix
ResetAssertedLevel
ResetInputPort
ResetLength
ResetType
ResetValue
SafeZeroConcat
SimulatorFlags
SplitArchFilePostfix
SplitEntityArch
SplitEntityFilePostfix
TargetDirectory
TargetLanguage
TestBenchClockEnableDelay
TestBenchDataPostFix
TestBenchPostFix
TestBenchReferencePostFix
Traceability
UseAggregatesForConst
UserComment
UseRisingEdge
UseVerilogTimescale
VectorPrefix
Verbosity
VerilogFileExtension
VHDLFileExtension

Property Reference

BlockGenerateLabel

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