Property Reference

Alphabetical List

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Language Selection Properties Properties for selecting language of generated HDL code File Naming and Location Properties Properties that name and specify location of generated files Reset Properties Properties that specify reset signals in generated code Header Comment and General Naming Properties Properties affecting generation of header comments and process, module, component instance, and other name strings Script Generation Properties Properties affecting generation of script files for simulation and synthesis tools Port Properties Properties that specify port characteristics in generated code Advanced Coding Properties Advanced HDL coding properties Test Bench Properties Properties that specify generated test bench code Generated Model Properties Properties for controlling naming and appearance of generated models

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Language Selection Properties

TargetLanguage

Specify HDL language to use for generated code

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File Naming and Location Properties

HDLMapPostfix	Specify postfix string appended to file name for generated mapping file
TargetDirectory	Identify directory into which generated output files are written
VerilogFileExtension	Specify file type extension for generated Verilog files
VHDLFileExtension	Specify file type extension for generated VHDL files

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Reset Properties

Oversampling	Specify frequency of global oversampling clock as a multiple of the model's base rate
ResetAssertedLevel	Specify asserted (active) level of reset input signal
ResetLength	Define length of time (in clock cycles) during which reset is asserted
ResetType	Specify whether to use asynchronous or synchronous reset logic when generating HDL code for registers
ResetValue	Specify constant value to which test bench forces reset input signals

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Header Comment and General Naming Properties

ClockProcessPostfix	Specify string to append to HDL clock process names
ComplexImagPostfix	Specify string to append to imaginary part of complex signal names
ComplexRealPostfix	Specify string to append to real part of complex signal names
EntityConflictPostfix	Specify string to append to duplicate VHDL entity or Verilog module names
InstancePrefix	Specify string prefixed to generated component instance names
PackagePostfix	Specify string to append to specified model or subsystem name to form name of package file
ReservedWordPostfix	Specify string appended to identifiers for entities, signals, constants, or other model elements that conflict with VHDL or Verilog reserved words
SplitArchFilePostfix	Specify string to append to specified name to form name of file containing model's VHDL architecture
SplitEntityArch	Specify whether generated VHDL entity and architecture code is written to single VHDL file or to separate files
SplitEntityFilePostfix	Specify string to append to specified model name to form name of generated VHDL entity file
VectorPrefix	Specify string prefixed to vector names in generated code

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Script Generation Properties

EDAScriptGeneration	Enable or disable generation of script files for third-party tools
HDLCompileFilePostfix	Specify postfix string appended to file name for generated Mentor Graphics ModelSim compilation scripts
HDLCompileInit	Specify string written to initialization section of compilation script
HDLCompileTerm	Specify string written to termination section of compilation script
HDLCompileVerilogCmd	Specify command string written to compilation script for Verilog files
HDLCompileVHDLCmd	Specify command string written to compilation script for VHDL files
HDLSimCmd	Specify simulation command written to simulation script
HDLSimFilePostfix	Specify postfix string appended to file name for generated Mentor Graphics ModelSim simulation scripts
HDLSimInit	Specify string written to initialization section of simulation script
HDLSimTerm	Specify string written to termination section of simulation script
HDLSimViewWaveCmd	Specify waveform viewing command written to simulation script
HDLSynthCmd	Specify command written to synthesis script
HDLSynthFilePostfix	Specify postfix string appended to file name for generated Synplify synthesis scripts
HDLSynthInit	Specify string written to initialization section of synthesis script
HDLSynthTerm	Specify string written to termination section of synthesis script

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Port Properties

ClockEnableInputPort	Name HDL port for model's clock enable input signals
ClockEnableOutputPort	Specify name of clock enable output port
ClockInputPort	Name HDL port for model's clock input signals
EnablePrefix	Specify base name string for internal clock enables in generated code
InputType	Specify HDL data type for model's input ports
OutputType	Specify HDL data type for model's output ports
ResetInputPort	Name HDL port for model's reset input

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Advanced Coding Properties

BlockGenerateLabel	Specify string to append to block labels used for HDL GENERATE statements
CastBeforeSum	Enable or disable type casting of input values for addition and subtraction operations before execution of operation
CheckHDL	Check model or subsystem for HDL code generation compatibility
HDLControlFiles	Attach code generation control file to model
InlineConfigurations	Specify whether generated VHDL code includes inline configurations
InstanceGenerateLabel	Specify string to append to instance section labels in VHDL GENERATE statements
LoopUnrolling	Specify whether VHDL FOR and GENERATE loops are unrolled and omitted from generated VHDL code
MulticyclePathInfo	Generate text file that reports multicycle path constraint information, for use with synthesis tools.
OptimizeTimingController	Optimize timing controller entity for speed and code size by implementing separate counters per rate
OutputGenerateLabel	Specify string that labels output assignment block for VHDL GENERATE statements
PipelinePostfix	Specify string to append to names of input or output pipeline registers generated for pipelined block implementations
RequirementComments	Enable or disable generation of hyperlinked requirements comments in HTML code generation reports
SafeZeroConcat	Specify syntax for concatenated zeros in generated VHDL code
Traceability	Enable or disable creation of HTML code generation report with code-to-model and model-to-code hyperlinks
UseAggregatesForConst	Specify whether all constants are represented by aggregates, including constants that are less than 32 bits
UserComment	Specify comment line in header of generated HDL and test bench files
UseRisingEdge	Specify VHDL coding style used to check for rising edges when operating on registers
UseVerilogTimescale	Use compiler `timescale directives in generated Verilog code
Verbosity	Specify level of detail for messages displayed during code generation

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Test Bench Properties

ClockHighTime	Specify period, in nanoseconds, during which test bench drives clock input signals high (1)
ClockLowTime	Specify period, in nanoseconds, during which test bench drives clock input signals low (0)
ForceClock	Specify whether test bench forces clock input signals
ForceClockEnable	Specify whether test bench forces clock enable input signals
ForceReset	Specify whether test bench forces reset input signals
GenerateCoSimBlock	Generate model containing HDL Cosimulation block(s) for use in testing DUT
GenerateCoSimModel	Generate model containing HDL Cosimulation block for use in testing DUT
HoldInputDataBetweenSamples	Specify how long subrate signal values are held in valid state
HoldTime	Specify hold time for input signals and forced reset input signals
IgnoreDataChecking	Specify number of samples during which output data checking is suppressed
InitializeTestBenchInputs	Specify initial value driven on test bench inputs before data is asserted to DUT
MultifileTestBench	Divide generated test bench into helper functions, data, and HDL test bench code files
SimulatorFlags	Specify simulator flags to apply to generated compilation scripts
TestBenchClockEnableDelay	Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable
TestBenchDataPostFix	Specify suffix added to test bench data file name when generating multi-file test bench
TestBenchPostFix	Specify suffix to test bench name
TestBenchReferencePostFix	Specify string appended to names of reference signals generated in test bench code

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Generated Model Properties

CodeGenerationOutput	Control production of generated code and display of generated model
Generatedmodelname	Specify name of generated model
Generatedmodelnameprefix	Specify prefix to name of generated model
Highlightancestors	Highlight ancestors of blocks in generated model that differ from original model
Highlightcolor	Specify color for highlighted blocks in generated model

Custom Script Generation

Properties — Alphabetical List

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