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Complex imaginary part postfix Represent constant values by aggregates Use "rising_edge" for registers |
The Global Settings pane lets you set options to specify detailed characteristics of the generated code, such as HDL element naming and whether certain optimizations are applied.
Specify whether to use asynchronous or synchronous reset logic when generating HDL code for registers.
Default: Asynchronous
| Property: ResetType |
| Type: string |
| Value: 'async' | 'sync' |
| Default: 'async' |
Specify whether the asserted (active) level of reset input signal is active-high or active-low.
Default: Active-high
Asserted (active) level of reset input signal is active-high (1).
Asserted (active) level of reset input signal is active-low (0).
| Property: ResetAssertedLevel |
| Type: string |
| Value: 'active-high' | 'active-low' |
| Default: 'active-high' |
Specify the name for the clock input port in generated HDL code.
Default: clk
Enter a string value to be used as the clock signal name in generated HDL code. If you specify a string that is a VHDL or Verilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.
| Property: ClockInputPort |
| Type: string |
| Value: Any identifier that is legal in the target language |
| Default: 'clk' |
Specify the name for the clock enable input port in generated HDL code.
Default: clk_enable
Enter a string value to be used as the clock enable input port name in generated HDL code. If you specify a string that is a VHDL or Verilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.
The clock enable input signal is asserted active-high (1). Thus, the input value must be high for the generated entity's registers to be updated.
| Property: ClockEnableInputPort |
| Type: string |
| Value: Any identifier that is legal in the target language |
| Default: 'clk_enable' |
Specify frequency of global oversampling clock as a multiple of the model's base rate.
Default: 1
Oversampling factor specifies the oversampling factor of a global oversampling clock. The oversampling factor expresses the desired rate of the global oversampling clock as a multiple of your model's base rate.
When you specify the Oversampling factor for a global oversampling clock, note these requirements:
The oversampling factor must be an integer greater than or equal to 1.
The default value is 1. In the default case, the coder does not generate a global oversampling clock is generated.
In a multirate DUT, all other rates in the DUT must divide evenly into the global oversampling rate.
| Property: Oversampling |
| Type: int |
| Value: integer greater than or equal to 1 |
| Default: 1 |
| Generating a Global Oversampling Clock |
| Oversampling |
Enter the name for the reset input port in generated HDL code.
Default: reset
Enter a string value to be used as the reset input port name in generated HDL code. If you specify a string that is a VHDL or Verilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.
If the reset asserted level is set to active-high, the reset input signal is asserted active-high (1) and the input value must be high (1) for the entity's registers to be reset. If the reset asserted level is set to active-low, the reset input signal is asserted active-low (0) and the input value must be low (0) for the entity's registers to be reset.
| Property: ResetInputPort |
| Type: string |
| Value: Any identifier that is legal in the target language |
| Default: 'reset' |
Specify comment lines in header of generated HDL and test bench files.
Default: None
Text entered in this field generates a comment line in the header of generated model and test bench files. The code generator adds leading comment characters as appropriate for the target language. When newlines or linefeeds are included in the string, the code generator emits single-line comments for each newline.
| Property: UserComment |
| Type: string |
Specify the file-name extension for generated Verilog files.
Default: .v
This field specifies the file-name extension for generated Verilog files.
This option is enabled when the target language (specified by the Language option) is Verilog.
| Property: VerilogFileExtension |
| Type: string |
| Default: '.v' |
Specify the file-name extension for generated VHDL files.
Default: .vhd
This field specifies the file-name extension for generated VHDL files.
This option is enabled when the target language (specified by the Language option) is VHDL.
| Property: VHDLFileExtension |
| Type: string |
| Default: '.vhd' |
Specify the string used to resolve duplicate VHDL entity or Verilog module names in generated code.
Default: _block
The specified postfix resolves duplicate VHDL entity or Verilog module names. For example, in the default case, if the coder detects two entities with the name MyFilt, the coder names the first entity MyFilt and the second instance MyFilt_entity.
| Property: EntityConflictPostfix |
| Type: string |
| Value: Any string that is legal in the target language |
| Default: '_block' |
Specify a string to append to the model or subsystem name to form name of a package file.
Default: _pkg
The coder applies this option only if a package file is required for the design.
This option is enabled when:
The target language (specified by the Language option) is VHDL.
The target language (specified by the Language option) is Verilog, and the Multi-file test bench option is selected.
| Property: PackagePostfix |
| Type: string |
| Value: Any string value that is legal in a VHDL package file name |
| Default: '_pkg' |
Specify a string to append to value names, postfix values, or labels that are VHDL or Verilog reserved words.
Default: _rsvd
The reserved word postfix is applied to identifiers (for entities, signals, constants, or other model elements) that conflict with VHDL or Verilog reserved words. For example, if your generating model contains a signal named mod, the coder adds the postfix _rsvd to form the name mod_rsvd.
| Property: ReservedWordPostfix |
| Type: string |
| Default: '_rsvd' |
Specify whether generated VHDL entity and architecture code is written to a single VHDL file or to separate files.
Default: Off
On VHDL entity and architecture definitions are written to separate files.
OffVHDL entity and architecture code is written to a single VHDL file.
The names of the entity and architecture files derive from the base file name (as specified by the generating model or subsystem name). By default, postfix strings identifying the file as an entity (_entity) or architecture (_arch) are appended to the base file name. You can override the default and specify your own postfix string.
For example, instead of all generated code residing in MyFIR.vhd, you can specify that the code reside in MyFIR_entity.vhd and MyFIR_arch.vhd.
This option is enabled when the target language (specified by the Language option) is Verilog.
Selecting this option enables the following parameters:
Split entity file postfix
Split architecture file postfix
| Property: SplitEntityArch |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'off' |
Enter a string to be appended to the model name to form the name of a generated VHDL entity file.
Default: _entity
This parameter is enabled by Split entity and architecture.
| Property: SplitEntityFilePostfix |
| Type: string |
| Default: '_entity' |
Enter a string to be appended to the model name to form the name of a generated VHDL architecture file.
Default: _arch
This parameter is enabled by Split entity and architecture.
| Property: SplitArchFilePostfix |
| Type: string |
| Default: '_arch' |
Specify a string to append to HDL clock process names.
Default: _process
The coder uses process blocks for register operations. The label for each of these blocks is derived from a register name and the postfix _process. For example, the coder derives the label delay_pipeline_process from the register name delay_pipeline and the default postfix string _process.
| Property: ClockProcessPostfix |
| Type: string |
| Default: '_process' |
Specify the base name string for internal clock enables and other flow control signals in generated code.
Default: 'enb'
Where only a single clock enable is generated, Enable prefix specifies the signal name for the internal clock enable signal.
In some cases, multiple clock enables are generated (for example, when a cascade block implementation for certain blocks is specified). In such cases, Enable prefix specifies a base signal name for the first clock enable that is generated. For other clock enable signals, numeric tags are appended to Enable prefix to form unique signal names. For example, the following code fragment illustrates two clock enables that were generated when Enable prefix was set to 'test_clk_enable':
COMPONENT Timing_Controller
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
test_clk_enable : OUT std_logic;
test_clk_enable_5_1_0 : OUT std_logic
);
END COMPONENT;| Property: EnablePrefix |
| Type: string |
| Default: 'enb' |
Specify string to append to names of input or output pipeline registers generated for pipelined block implementations.
Default: '_pipe'
Using a control file, you can specify a generation of input and/or output pipeline registers for selected blocks. The coder appends the string specified by the Pipeline postfix option when generating code for such pipeline registers.
| Property: PipelinePostfix |
| Type: string |
| Default: '_pipe' |
Specify string to append to real part of complex signal names.
Default: '_re'
Enter a string to be appended to the names generated for the real part of complex signals.
| Property: ComplexRealPostfix |
| Type: string |
| Default: '_re' |
Specify string to append to imaginary part of complex signal names.
Default: '_im'
Enter a string to be appended to the names generated for the imaginary part of complex signals.
| Property: ComplexImagPostfix |
| Type: string |
| Default: '_im' |
Specify the HDL data type for the model's input ports.
For VHDL, the options are:
Default: std_logic_vector
Specifies VHDL type STD_LOGIC_VECTOR.
Specifies VHDL type SIGNED or UNSIGNED.
For Verilog, the options are:
Default: wire
In generated Verilog code, the data type for all ports is 'wire'. Therefore, Input data type is disabled when the target language is Verilog.
This option is enabled when the target language (specified by the Language option) is VHDL.
| Property: InputType |
| Type: string |
| Value: (for VHDL)'std_logic_vector' | 'signed/unsigned' |
| (for Verilog) 'wire' |
| Default: (for VHDL) 'std_logic_vector' |
| (for Verilog) 'wire' |
Specify the HDL data type for the model's output ports.
For VHDL, the options are:
Default: Same as input data type
Specifies that output ports have the same type specified by Input data type.
Specifies VHDL type STD_LOGIC_VECTOR.
Specifies VHDL type SIGNED or UNSIGNED.
For Verilog, the options are:
Default: wire
In generated Verilog code, the data type for all ports is 'wire'. Therefore, Output data type is disabled when the target language is Verilog.
This option is enabled when the target language (specified by the Language option) is VHDL.
| Property: OutputType |
| Type: string |
| Value: (for VHDL)'std_logic_vector' | 'signed/unsigned' |
| (for Verilog) 'wire' |
| Default: If the property is left unspecified, output ports have the same type specified by InputType. |
Specify the name for the generated clock enable output.
Default: ce_out
A clock enable output is generated when the design requires one.
| Property: ClockEnableOutputPort |
| Type: string |
| Default: 'ce_out' |
Specify whether all constants in VHDL code are represented by aggregates, including constants that are less than 32 bits.
Default: Off
On The coder represents all constants as aggregates. The following VHDL constant declarations show a scalar less than 32 bits represented as an aggregate:
GainFactor_gainparam <= (14 => '1', OTHERS => '0');
OffThe coder represents constants less than 32 bits as scalars and constants greater than or equal to 32 bits as aggregates. The following VHDL code was generated by default for a value less than 32 bits:
GainFactor_gainparam <= to_signed(16384, 16);
This option is enabled when the target language (specified by the Language option) is VHDL.
| Property: UseAggregatesForConst |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'off' |
Specify whether or not generated code uses the VHDL rising_edge function to check for rising edges when operating on registers.
Default: Off
On Generated code uses the VHDL rising_edge function to check for rising edges when operating on registers.
OffGenerated code checks for clock events when operating on registers.
This option is enabled when the target language (specified by the Language option) is VHDL.
| Property: UseRisingEdge |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'off' |
Specify whether VHDL FOR and GENERATE loops are unrolled and omitted from generated VHDL code.
Default: Off
On Unroll and omit FOR and GENERATE loops from the generated VHDL code. (In Verilog code, loops are always unrolled.)
OffInclude FOR and GENERATE loops in the generated VHDL code.
If you are using an electronic design automation (EDA) tool that does not support GENERATE loops, select this option to omit loops from your generated VHDL code.
This option is enabled when the target language (specified by the Language option) is VHDL.
| Property: LoopUnrolling |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'off' |
Specify whether operands in addition and subtraction operations are type cast to the result type before executing the operation.
Default: On
On Typecast input values in addition and subtraction operations to the result type before operating on the values.
OffPreserve the types of input values during addition and subtraction operations and then convert the result to the result type.
| Property: CastBeforeSum |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'on' |
Specify use of compiler `timescale directives in generated Verilog code.
Default: On
On Use compiler `timescale directives in generated Verilog code.
OffSuppress the use of compiler `timescale directives in generated Verilog code.
The `timescale directive provides a way of specifying different delay values for multiple modules in a Verilog file. This setting does not affect the generated test bench.
This option is enabled when the target language (specified by the Language option) is Verilog.
| Property: UseVerilogTimescale |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'on' |
Specify whether generated VHDL code includes inline configurations.
Default: On
On Include VHDL configurations in any file that instantiates a component.
OffSuppress the generation of configurations and require user-supplied external configurations. Use this setting if you are creating your own VHDL configuration files.
HDL configurations can be either inline with the rest of the VHDL code for an entity or external in separate VHDL source files. By default, the coder includes configurations for a model within the generated VHDL code. If you are creating your own VHDL configuration files, suppress the generation of inline configurations.
This option is enabled when the target language (specified by the Language option) is VHDL.
| Property: InlineConfigurations |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'on' |
Specify use of syntax for concatenated zeros in generated VHDL code.
Default: On
On Use the type-safe syntax, '0' & '0', for concatenated zeros. Typically, this syntax is preferred.
OffUse the syntax "000000..." for concatenated zeros. This syntax can be easier to read and more compact, but it can lead to ambiguous types.
This option is enabled when the target language (specified by the Language option) is VHDL.
| Property: SafeZeroConcat |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'on' |
Optimize timing controller entity for speed and code size by implementing separate counters per rate.
Default: On
On The coder generates multiple counters (one counter for each rate in the model) in the timing controller code. The benefit of this optimization is that it generates faster logic, and the size of the generated code is usually much smaller.
OffThe coder generates a timing controller that uses one counter to generate all rates in the model.
A timing controller code file (Timing_Controller.vhd or Timing_Controller.v) is generated if required by the design, for example:
When code is generated for a multirate model
When a cascade block implementation for certain blocks is specified
This file contains a module defining timing signals (clock, reset, external clock enable inputs and clock enable output) in a separate entity or module. In a multirate model, the timing controller entity generates the required rates from a single master clock using one or more counters and multiple clock enables.
| Property: OptimizeTimingController |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'on' |
Omit generation of clock enable logic for single-rate designs.
Default: Off
On For single-rate models, omit generation of clock enable logic wherever possible. The following VHDL code example does not define or examine a clock enable signal. When the clock signal (clk) goes high, the current signal value is output.
Unit_Delay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Unit_Delay_out1 <= to_signed(0, 32);
ELSIF clk'EVENT AND clk = '1' THEN
Unit_Delay_out1 <= In1_signed;
END IF;
END PROCESS Unit_Delay_process; OffGenerate clock enable logic. The following VHDL code extract represents a register with a clock enable (enb)
Unit_Delay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Unit_Delay_out1 <= to_signed(0, 32);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Unit_Delay_out1 <= In1_signed;
END IF;
END IF;
END PROCESS Unit_Delay_process;In some cases, the coder emits clock enables even when Minimize clock enables is selected. These cases are:
Registers inside Enabled, State-Enabled, and Triggered subsystems.
Multi-rate models.
The coder always emits clock enables for the following blocks:
commseqgen2/PN Sequence Generator
dspsigops/NCO
dspsrcs4/Sine Wave
hdldemolib/HDL FFT
built-in/DiscreteFir
dspmlti4/CIC Decimation
dspmlti4/CIC Interpolation
dspmlti4/FIR Decimation
dspmlti4/FIR Interpolation
dspadpt3/LMS Filter
dsparch4/Biquad Filter
dsparch4/Digital Filter
| Property: MinimizeClockEnable |
| Type: string |
| Value: 'on' | 'off' |
| Default: 'off' |
 | HDL Coder Pane: General | HDL Coder Pane: Test Bench |  |
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