HDL Coder Pane: Test Bench :: Code Generation Options in the Simulink HDL Coder GUI (Simulink® HDL Coder™)

HDL Coder Pane: Test Bench

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Test Bench Overview HDL test bench Cosimulation blocks Cosimulation model for use with: Test bench name postfix Force clock Clock high time (ns) Clock low time (ns) Hold time (ns) Setup time (ns) Force clock enable Clock enable delay (in clock cycles) Force reset Reset length (in clock cycles) Hold input data between samples Initialize test bench inputs Multi-file test bench Test bench reference postfix Test bench data file name postfix Ignore output data checking (number of samples)

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Test Bench Overview

HDL test bench

Cosimulation blocks

Cosimulation model for use with:

Test bench name postfix

Clock enable delay (in clock cycles)

Force reset

Reset length (in clock cycles)

Hold input data between samples

Initialize test bench inputs

Multi-file test bench

Test bench reference postfix

Test bench data file name postfix

Ignore output data checking (number of samples)

Test Bench Overview

The Test Bench pane lets you set options that determine characteristics of generated test bench code.

Generate Test Bench Button

The Generate Test Bench button initiates test bench generation for the system selected in the Generate HDL for menu. See also makehdltb.

HDL test bench

Enable generation of an HDL test bench.

Settings

Default: On

On: Generate HDL test bench code.
Off: Suppress generation of HDL test bench code.

Dependencies

This check box enables all options in the Configuration section of the Test Bench pane.

Command-Line Information

To generate test bench code from the command line, use themakehdltb function.

Cosimulation blocks

Generate a model containing HDL Cosimulation block(s) for use in testing the DUT.

Settings

Default: Off

On

When you select this option, the coder generates and opens a model that contains one or more HDL Cosimulation blocks. The coder generates cosimulation blocks if your installation includes one or more of the following:

EDA Simulator Link for use with Mentor Graphics^® ModelSim^®
EDA Simulator Link for use with Cadence Incisive
EDA Simulator Link for use with Synopsys Discovery

The coder configures the generated HDL Cosimulation blocks to conform to the port and data type interface of the DUT selected for code generation. By connecting an HDL Cosimulation block to your model in place of the DUT, you can cosimulate your design with the desired simulator.

Off

Do not generate HDL Cosimulation blocks.

Dependencies

This check box enables all other options in the Configuration section of the Test Bench pane.

Command-Line Information

Property: GenerateCoSimBlock

Type: string

Value: 'on' | 'off'

Default: 'off'

Cosimulation model for use with:

Generate model containing HDL Cosimulation block for cosimulation

Settings

Default: Off

On

Selecting this option enables the dropdown menu to the right of the check box. Select one of the following options from the menu:

Mentor Graphics ModelSim: This option is the default. If your installation includes EDA Simulator Link for use with Mentor Graphics ModelSim, the coder generates and opens a Simulink model that contains an HDL Cosimulation block forMentor Graphics ModelSim.
Cadence Incisive: If your installation includes EDA Simulator Link for use with Cadence Incisive, the coder generates and opens a Simulink model that contains an HDL Cosimulation block forCadence Incisive.

Off

Do not generate HDL Cosimulation model.

Command-Line Information

Property: GenerateCosimModel

Type: string

Value: 'on' | 'off'

Default: 'off'

Test bench name postfix

Specify a suffix appended to the test bench name.

Settings

Default: _tb

For example, if the name of your DUT is my_test, the coder adds the default postfix _tb to form the name my_test_tb.

Command-Line Information

Property: TestBenchPostFix

Type: string

Default: '_tb'

Force clock

Specify whether the test bench forces clock input signals.

Settings

Default: On

On: The test bench forces the clock input signals. When this option is selected, the clock high and low time settings control the clock waveform.
Off: A user-defined external source forces the clock input signals.

Dependencies

This property enables the Clock high time and Clock high time options.

Command-Line Information

Property: ForceClock

Type: string

Value: 'on' | 'off'

Default: 'on'

Clock high time (ns)

Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1).

Settings

Default: 5

The Clock high time and Clock low time properties define the period and duty cycle for the clock signal. Using the defaults, the clock signal is a square wave (50% duty cycle) with a period of 10 ns.

Dependencies

This parameter is enabled when Force clock is selected.

Command-Line Information

Property: ClockHighTime

Type: integer or double (with a maximum of 6 significant digits after the decimal point)

Default: 5

Clock low time (ns)

Specify the period, in nanoseconds, during which the test bench drives clock input signals low (0).

Settings

Default: 5

Dependencies

This parameter is enabled when Force clock is selected.

Command-Line Information

Property: ClockLowTime

Type: integer or double (with a maximum of 6 significant digits after the decimal point)

Default: 5

Hold time (ns)

Specify a hold time, in nanoseconds, for input signals and forced reset input signals.

Settings

Default: 2 (given the default clock period of 10 ns)

The hold time defines the number of nanoseconds that reset input signals and input data are held past the clock rising edge. The hold time is expressed as a positive integer or double (with a maximum of 6 significant digits after the decimal point).

Tips

The specified hold time must be less than the clock period (specified by the Clock high time and Clock low time properties).
This option applies to reset input signals only if Force reset is selected.

Command-Line Information

Property: HoldTime

Type: integer or double (with a maximum of 6 significant digits after the decimal point)

Value: A positive integer

Default: 2

Setup time (ns)

Display setup time for data input signals.

Settings

Default: None

This is a display-only field, showing a value computed as (clock period - HoldTime) in nanoseconds.

Dependency

The value displayed in this field depends on the clock rate and the values of the Hold time property.

Command-Line Information

Because this is a display-only field, there is no corresponding command-line property.

Force clock enable

Specify whether the test bench forces clock enable input signals.

Settings

Default: On

On: The test bench forces the clock enable input signals to active-high (1) or active-low (0), depending on the setting of the clock enable input value.
Off: A user-defined external source forces the clock enable input signals.

Dependencies

This property enables the Clock enable delay (in clock cycles) option.

Command-Line Information

Property: ForceClockEnable

Type: string

Value: 'on' | 'off'

Default: 'on'

Clock enable delay (in clock cycles)

Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable.

Settings

Default: 1

The Clock enable delay (in clock cycles) property defines the number of clock cycles elapsed between the time the reset signal is deasserted and the time the clock enable signal is first asserted. In the figure below, the reset signal (active-high) deasserts after 2 clock cycles and the clock enable asserts after a clock enable delay of 1 cycle (the default).

Dependency

This parameter is enabled when Force clock enable is selected.

Command-Line Information

Property: TestBenchClockEnableDelay

Type: integer

Default: 1

Force reset

Specify whether the test bench forces reset input signals.

Settings

Default: On

On: The test bench forces the reset input signals.
Off: A user-defined external source forces the reset input signals.

Tips

If you select this option, you can use the Hold time option to control the timing of a reset.

Command-Line Information

Property: ForceReset

Type: string

Value: 'on' | 'off'

Default: 'on'

Reset length (in clock cycles)

Define length of time (in clock cycles) during which reset is asserted.

Settings

Default: 2

The Reset length (in clock cycles) property defines the number of clock cycles during which reset is asserted. Reset length (in clock cycles) must be an integer greater than or equal to 0. The following figure illustrates the default case, in which the reset signal (active-high) is asserted for 2 clock cycles.

Dependency

This parameter is enabled when Force reset is selected.

Command-Line Information

Property: Resetlength

Type: integer

Default: 2

Hold input data between samples

Specify how long subrate signal values are held in valid state.

Settings

Default: On

On: Data values for subrate signals are held in a valid state across N base-rate clock cycles, where N is the number of base-rate clock cycles that elapse per subrate sample period. (N is >= 2.)
Off: Data values for subrate signals are held in a valid state for only one base-rate clock cycle. For the subsequent base-rate cycles, data is in an unknown state (expressed as 'X') until leading edge of the next subrate sample period.

Tip

In most cases, the default (On) is the correct setting for Hold input data between samples. This setting matches the behavior of a Simulink simulation, in which subrate signals are always held valid through each base-rate clock period.

In some cases (for example modeling memory or memory interfaces), it is desirable to clear Hold input data between samples. In this way you can obtain diagnostic information about when data is in an invalid ('X') state.

Command-Line Information

Property: HoldInputDataBetweenSamples

Type: string

Value: 'on' | 'off'

Default: 'on'

Initialize test bench inputs

Specify initial value driven on test bench inputs before data is asserted to DUT.

Settings

Default: Off

On: Initial value driven on test bench inputs is'0'.
Off: Initial value driven on test bench inputs is 'X' (unknown).

Command-Line Information

Property: InitializeTestBenchInputs

Type: string

Value: 'on' | 'off'

Default: 'off'

Multi-file test bench

Divide generated test bench into helper functions, data, and HDL test bench code files.

Settings

Default: Off

On

Write separate files for test bench code, helper functions, and test bench data. The file names are derived from the name of the DUT, the Test bench name postfix property, and the Test bench data file name postfix property as follows:

DUTname_TestBenchPostfix_TestBenchDataPostfix

For example, if the DUT name is symmetric_fir, and the target language is VHDL, the default test bench file names are:

symmetric_fir_tb.vhd: test bench code
symmetric_fir_tb_pkg.vhd: helper functions package
symmetric_fir_tb_data.vhd: data package

If the DUT name is symmetric_fir and the target language is Verilog, the default test bench file names are:

symmetric_fir_tb.v: test bench code
symmetric_fir_tb_pkg.v: helper functions package
symmetric_fir_tb_data.v: test bench data

Off

Write a single test bench file containing all HDL test bench code and helper functions and test bench data.

Dependency

When this property is selected, Test bench data file name postfix is enabled.

Command-Line Information

Property: MultifileTestBench

Type: string

Value: 'on' | 'off'

Default: 'off'

Test bench reference postfix

Specify a string appended to names of reference signals generated in test bench code.

Settings

Default: '_ref'

Reference signal data is represented as arrays in the generated test bench code. The string specified by Test bench reference postfix is appended to the generated signal names.

Command-Line Information

Parameter: TestBenchReferencePostFix

Type: string

Default: '_ref'

Test bench data file name postfix

Specify suffix added to test bench data file name when generating multi-file test bench.

Settings

Default:'_data'

The coder applies the Test bench data file name postfix string only when generating a multi-file test bench (i.e., when Multi-file test bench is selected).

For example, if the name of your DUT is my_test, and Test bench name postfix has the default value _tb, the coder adds the postfix _data to form the test bench data file name my_test_tb_data.

Dependency

This parameter is enabled by Multi-file test bench.

Command-Line Information

Property: TestBenchDataPostFix

Type: string

Default: '_data'

Ignore output data checking (number of samples)

Specify number of samples during which output data checking is suppressed.

Settings

Default: 0

The value must be a positive integer.

When the value N of Ignore output data checking (number of samples) is greater than zero, the test bench suppresses output data checking for the first N output samples after the clock enable output (ce_out) is asserted.

When using pipelined block implementations, output data may be in an invalid state for some number of samples. To avoid spurious test bench errors, determine this number and set Ignore output data checking (number of samples) accordingly.

Be careful to specify N correctly as a number of samples, not as a number of clock cycles. For a single-rate model, these are equivalent, but they are not equivalent for a multirate model.

You should use Ignore output data checking (number of samples) in cases where there is any state (register) initial condition in the HDL code that does not match the Simulink state, including the following specific cases:

When you specify the 'DistributedPipelining','on' parameter for the Embedded MATLAB Function block (see Distributed Pipeline Insertion)
When you specify the {'ResetType','None'} parameter for any of the following block types:
- Integer Delay
- Tapped Delay
- Unit Delay
- Unit Delay Enabled
When generating a black box interface to existing manually written HDL code

Command-Line Information

Property: IgnoreDataChecking

Type: integer

Default: 0

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