Generating HDL Code Using the Command Line Interface :: Introduction to HDL Code Generation (Simulink® HDL Coder™)

Generating HDL Code Using the Command Line Interface

On this page…
Overview Creating a Folder and Local Model File Initializing Model Parameters with hdlsetup Generating a VHDL Entity from a Subsystem Generating VHDL Test Bench Code Verifying Generated Code Generating a Verilog Module and Test Bench

On this page…

Overview

Creating a Folder and Local Model File

Initializing Model Parameters with hdlsetup

Generating a VHDL Entity from a Subsystem

Generating VHDL Test Bench Code

Verifying Generated Code

Generating a Verilog Module and Test Bench

Overview

This exercise provides a step-by-step introduction to code and test bench generation commands, their arguments, and the files created by the code generator. The exercise assumes that you have familiarized yourself with the demo model (see The sfir_fixed Demo Model).

Creating a Folder and Local Model File

Make a local copy of the demo model and store it in a working folder, as follows.

Start the MATLAB software.
Create a folder named sl_hdlcoder_work, for example:
```
mkdir C:\work\sl_hdlcoder_work
```
The sl_hdlcoder_work folder will store a local copy of the demo model and to store directories and code generated by the coder. The location of the folder does not matter, except that it should not be within the MATLAB directory tree.
Make the sl_hdlcoder_work folder your working folder, for example:
```
cd C:\work\sl_hdlcoder_work
```
To open the demo model, type the following command at the MATLAB prompt:
```
demos
```
The Help window opens. In the Demos pane on the left, click the + for Simulink. Then click the + for Simulink HDL Coder. Then double-click the list entry for the Symmetric FIR Filter Demo.
The sfir_fixed model opens.
Select Save As from the Simulink File menu and save a local copy of sfir_fixed.mdl. to your working folder.
Leave the sfir_fixed model open and proceed to the next section.

Initializing Model Parameters with hdlsetup

Before generating code, you must set some parameters of the model. Rather than doing this manually, use the M-file utility, hdlsetup.m. The hdlsetup command uses the set_param function to set up models for HDL code generation quickly and consistently.

To set the model parameters:

At the MATLAB command prompt, type
```
hdlsetup('sfir_fixed')
```
Select Save from the File menu, to save the model with its new settings.

Before continuing with code generation, consider the settings that hdlsetup applies to the model.

hdlsetup configures the Solver options that are recommended or required by the coder. These are

Type: Fixed-step. (The coder currently supports variable-step solvers under limited conditions. See hdlsetup.)
Solver: Discrete (no continuous states). Other fixed-step solvers could be selected, but this option is usually the correct one for simulating discrete systems.
Tasking mode: SingleTasking. The coder does not currently support models that execute in multitasking mode.
Do not set Tasking mode to Auto.

hdlsetup also configures the model start and stop times and fixed-step size as follows:

Start Time: 0.0 s
Stop Time: 10 s
Fixed step size (fundamental periodic sample time): auto

If Fixed step size is set to auto the step size is chosen automatically, based on the sample times specified in the model. In the demo model, only the Signal From Workspace block specifies an explicit sample time (1 s); all other blocks inherit this sample time.

The model start and stop times determine the total simulation time. This in turn determines the size of data arrays that are generated to provide stimulus and output data for generated test benches. For the demo model, computation of 10 seconds of test data does not take a significant amount of time. Computation of sample values for more complex models can be time consuming. In such cases, you may want to decrease the total simulation time.

The remaining parameters set by hdlsetup affect error severity levels, data logging, and model display options. If you want to view the complete set of model parameters affected by hdlsetup, open hdlsetup.m in the MATLAB Editor.

The model parameter settings provided by hdlsetup are intended as useful defaults, but they may not be appropriate for all your applications. For example, hdlsetup sets a default Simulation stop time of 10 s. A total simulation time of 1000 s would be more realistic for a test of the sfir_fixed demo model. If you would like to change the simulation time, enter the desired value into the Simulation stop time field of the Simulink window.

See the "Model Parameters" table in the "Model and Block Parameters" section of the Simulink documentation for a summary of user-settable model parameters.

Generating a VHDL Entity from a Subsystem

In this section, you will use the makehdl function to generate code for a VHDL entity from the symmetric_fir subsystem of the demo model. makehdl also generates script files for third-party HDL simulation and synthesis tools.

makehdl lets you specify numerous properties that control various features of the generated code. In this example, you will use defaults for all makehdl properties.

Before generating code, make sure that you have completed the steps described in Creating a Folder and Local Model File and Initializing Model Parameters with hdlsetup.

To generate code:

Select Current Folder from the Desktop menu in the MATLAB window. This displays the MATLAB Current Folder browser, which lets you easily access your working folder and the files that will be generated within it.
At the MATLAB prompt, type the command
```
makehdl('sfir_fixed/symmetric_fir')
```
This command directs the coder to generate code from the symmetric_fir subsystem within the sfir_fixed model, using default values for all properties.
As code generation proceeds, the coder displays progress messages. The process should complete successfully with the message
```
### HDL Code Generation Complete.
```
Observe that the names of generated files in the progress messages are hyperlinked. After code generation completes, you can click these hyperlinks to view the files in the MATLAB Editor.
makehdl compiles the model before generating code. Depending on model display options (such as port data types, etc.), the appearance of the model may change after code generation.
By default, makehdl generates VHDL code. Code files and scripts are written to a target folder. The default target folder is a subfolder of your working folder, named hdlsrc.
A folder icon for the hdlsrc folder is now visible in the Current Folder browser. To view generated code and script files, double-click the hdlsrc folder icon.
The files that makehdl has generated in the hdlsrc folder are
- symmetric_fir.vhd: VHDL code. This file contains an entity definition and RTL architecture implementing the symmetric_fir filter.
- symmetric_fir_compile.do: Mentor Graphics ModelSim compilation script (vcom command) to compile the generated VHDL code.
- symmetric_fir_synplify.tcl: Synplify synthesis script
- symmetric_fir_map.txt: Mapping file. This report file maps generated entities (or modules) to the subsystems that generated them (see Code Tracing Using the Mapping File).
To view the generated VHDL code in the MATLAB Editor, double-click the symmetric_fir.vhd file icon in the Current Folder browser.
At this point it is suggested that you study the ENTITY and ARCHITECTURE definitions while referring to HDL Code Generation Defaults in the makehdl reference documentation. The reference documentation describes the default naming conventions and correspondences between the elements of a model (subsystems, ports, signals, etc.) and elements of generated HDL code.
Before proceeding to the next section, close any files you have opened in the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your sl_hdlcoder_work folder.
Leave the sfir_fixed model open and proceed to the next section.

Generating VHDL Test Bench Code

In this section, you use the test bench generation function, makehdltb, to generate a VHDL test bench. The test bench is designed to drive and verify the operation of the symmetric_fir entity that was generated in the previous section. A generated test bench includes

Stimulus data generated by signal sources connected to the entity under test.
Output data generated by the entity under test. During a test bench run, this data is compared to the outputs of the VHDL model, for verification purposes.
Clock, reset, and clock enable inputs to drive the entity under test.
A component instantiation of the entity under test.
Code to drive the entity under test and compare its outputs to the expected data.

In addition, makehdltb generates Mentor Graphics ModelSim scripts to compile and execute the test bench.

This exercise assumes that your working folder is the same as that used in the previous section. This folder now contains an hdlsrc folder containing the previously generated code.

To generate a test bench:

At the MATLAB prompt, type the command
```
makehdltb('sfir_fixed/symmetric_fir')
```
This command generates a test bench that is designed to interface to and validate code generated from symmetric_fir (or from a subsystem with a functionally identical interface). By default, VHDL test bench code, as well as scripts, are generated in the hdlsrc target folder.
As test bench generation proceeds, the coder displays progress messages. The process should complete successfully with the message
```
### HDL TestBench Generation Complete.
```
To view generated test bench and script files, double-click the hdlsrc folder icon in the Current Folder browser. Alternatively, you can click the hyperlinked names of generated files in the code test bench generation progress messages.
The files generated by makehdltb are:
- symmetric_fir_tb.vhd: VHDL test bench code and generated test and output data.
- symmetric_fir_tb_compile.do: Mentor Graphics ModelSim compilation script (vcom commands). This script compiles and loads both the entity to be tested (symmetric_fir.vhd) and the test bench code (symmetric_fir_tb.vhd).
- symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to initialize the simulator, set up wave window signal displays, and run a simulation.
If you want to view the generated test bench code in the MATLAB Editor, double-click the symmetric_fir.vhd file icon in the Current Folder browser. You may want to study the code while referring to the makehdltb reference documentation, which describes the default actions of the test bench generator.
Before proceeding to the next section, close any files you have opened in the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your sl_hdlcoder_work folder.

Verifying Generated Code

You can now take the previously generated code and test bench to an HDL simulator for simulated execution and verification of results. See Simulating and Verifying Generated HDL Code for an example of how to use generated test bench and script files with the Mentor Graphics ModelSim simulator.

Generating a Verilog Module and Test Bench

The procedures for generating Verilog code differ only slightly from those for generating VHDL code. This section provides an overview of the command syntax and the generated files.

Generating a Verilog Module

By default, makehdl generates VHDL code. To override the default and generate Verilog code, you must pass in a property/value pair to makehdl, setting the TargetLanguage property to 'verilog', as in this example.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','verilog')

The previous command generates Verilog source code, as well as scripts for the simulation and the synthesis tools, in the default target folder, hdlsrc.

The files generated by this example command are:

symmetric_fir.v: Verilog code. This file contains a Verilog module implementing the symmetric_fir subsystem.
symmetric_fir_compile.do: Mentor Graphics ModelSim compilation script (vlog command) to compile the generated Verilog code.
symmetric_fir_synplify.tcl: Synplify synthesis script.
symmetric_fir_map.txt.: Mapping file. This report file maps generated entities (or modules) to the subsystems that generated them (see Code Tracing Using the Mapping File).

Generating and Executing a Verilog Test Bench

The makehdltb syntax for overriding the target language is exactly the same as that for makehdl. The following example generates Verilog test bench code to drive the Verilog module, symmetric_fir, in the default target folder.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','verilog')

The files generated by this example command are

symmetric_fir_tb.v: Verilog test bench code and generated test and output data.
symmetric_fir_tb_compile.do: Mentor Graphics ModelSim compilation script (vlog commands). This script compiles and loads both the entity to be tested (symmetric_fir.v) and the test bench code (symmetric_fir_tb.v).
symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to initialize the simulator, set up wave window signal displays, and run a simulation.

The following listing shows the commands and responses from a test bench session using the generated scripts:

ModelSim>vlib work
ModelSim> do symmetric_fir_tb_compile.do
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module symmetric_fir
# 
# Top level modules:
# 	symmetric_fir
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module symmetric_fir_tb
# 
# Top level modules:
# 	symmetric_fir_tb
ModelSim>do symmetric_fir_tb_sim.do
# vsim work.symmetric_fir_tb 
# Loading work.symmetric_fir_tb
# Loading work.symmetric_fir
# **** Test Complete. ****
# Break at 
C:/work/sl_hdlcoder_work/vlog_code/symmetric_fir_tb.v line 142
# Simulation Breakpoint:Break at
C:/work/sl_hdlcoder_work/vlog_code/symmetric_fir_tb.v line 142
# MACRO ./symmetric_fir_tb_sim.do PAUSED at line 14

The sfir_fixed Demo Model

Generating HDL Code Using the GUI

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