Simulating and Verifying Generated HDL Code

Note   This section requires the use of the Mentor Graphics ModelSim simulator.

This section assumes that you have generated code from the sfir_fixed demo model as described in either of the following exercises:

• Generating HDL Code Using the Command Line Interface

• Generating HDL Code Using the GUI

In this section you compile and run a simulation of the previous generated model and test bench code. The scripts generated by the coder let you do this with just a few simple commands. The procedure is the same, whether you generated code in the command line environment or in the GUI.

To run the simulation:

1. Start the Mentor Graphics ModelSim software.

2. Set the working folder to the folder in which you previously generated code.

   ModelSim>cd C:/work/sl_hdlcoder_work/hdlsrc
   

3. Use the generated compilation script to compile and load the generated model and text bench code. The following listing shows the command and responses.

   ModelSim>do symmetric_fir_tb_compile.do
   # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
   # -- Loading package standard
   # -- Loading package std_logic_1164
   # -- Loading package numeric_std
   # -- Compiling entity symmetric_fir
   # -- Compiling architecture rtl of symmetric_fir
   # Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
   # -- Loading package standard
   # -- Loading package std_logic_1164
   # -- Loading package numeric_std
   # -- Compiling package symmetric_fir_tb_pkg
   # -- Compiling package body symmetric_fir_tb_pkg
   # -- Loading package symmetric_fir_tb_pkg
   # -- Loading package symmetric_fir_tb_pkg
   # -- Compiling entity symmetric_fir_tb
   # -- Compiling architecture rtl of symmetric_fir_tb
   # -- Loading entity symmetric_fir
   

4. Use the generated simulation script to execute the simulation. The following listing shows the command and responses. The warning messages are benign.

   ModelSim>do  symmetric_fir_tb_sim.do
   # vsim work.symmetric_fir_tb 
   # Loading C:\Applications\ModelTech_6_0\win32/../std.standard
   # Loading C:\Applications\ModelTech_6_0\win32/../ieee.std_logic_1164(body)
   # Loading C:\Applications\ModelTech_6_0\win32/../ieee.numeric_std(body)
   # Loading work.symmetric_fir_tb_pkg(body)
   # Loading work.symmetric_fir_tb(rtl)
   # Loading work.symmetric_fir(rtl)
   # ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE
   #    Time: 0 ns  Iteration: 0  Instance: /symmetric_fir_tb
   .
   .
   .
   # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
   #    Time: 0 ns  Iteration: 1  Instance: /symmetric_fir_tb
   # ** Note: **************TEST COMPLETED **************
   #    Time: 140 ns  Iteration: 1  Instance: /symmetric_fir_tb

   The test bench termination message indicates that the simulation has run to completion successfully, without any comparison errors.

   # ** Note: **************TEST COMPLETED **************
   

5. The simulation script displays all inputs and outputs in the model (including the reference signals y_out_ref and delayed_x_out_ref) in the Mentor Graphics ModelSim wave window. The following figure shows the signals displayed in the wave window.

   

6. Exit the Mentor Graphics ModelSim simulator when you finish viewing signals.

7. Close any files you have opened in the MATLAB Editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your sl_hdlcoder_work folder.

Generating HDL Code Using the GUI

Code Generation Options in the Simulink HDL Coder GUI

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