Using Fixed-Point Bitwise Functions :: Generating HDL Code with the Embedded MATLAB Function Block (Simulink® HDL Coder™)

Using Fixed-Point Bitwise Functions

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Overview Bitwise Functions Supported for HDL Code Generation Bit Slice and Bit Concatenation Functions Shift and Rotate Functions

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Bitwise Functions Supported for HDL Code Generation

Bit Slice and Bit Concatenation Functions

Overview

The Embedded MATLAB Function block supports many bitwise functions that operate on fixed-point integers of arbitrary length. For general information on Embedded MATLAB bitwise functions, see Bitwise Operations in the Fixed-Point Toolbox documentation.

This section describes HDL code generation support for these functions. Bitwise Functions Supported for HDL Code Generation summarizes the supported functions, with notes that describe considerations specific to HDL code generation. Bit Slice and Bit Concatenation Functions and Shift and Rotate Functions provide usage examples, with corresponding Embedded MATLAB Function block code and generated HDL code.

The Bit Twiddlers/hdl_bit_ops block in the eml_hdl_design_patterns library provides further examples of how to use these functions for various bit manipulation operations.

Bitwise Functions Supported for HDL Code Generation

The following table summarizes Embedded MATLAB Function block bitwise functions that are supported for HDL code generation. The Description column notes considerations that are specific to HDL. The following conventions are used in the table:

a,b: Denote fixed-point integer operands.
idx: Denotes an index to a bit within an operand. Indexes can be scalar or vector, depending on the function.
Embedded MATLAB Function blocks follow the MATLAB (1-based) indexing conventions. In generated HDL code, such indexes are converted to zero-based indexing conventions.
lidx, ridx: denote indexes to the left and right boundaries delimiting bit fields. Indexes can be scalar or vector, depending on the function.
val: Denotes a Boolean value.

Note Indexes, operands, and values passed as arguments bitwise functions can be scalar or vector, depending on the function. See Bitwise Operations in the Fixed-Point Toolbox documentation for information on the individual functions.

Embedded MATLAB
Function Block Syntax Description See Also

bitand(a, b) Bitwise AND bitand

bitandreduce(a, lidx, ridx)
Bitwise AND of a field of consecutive bits within a. The field is delimited by lidx , ridx.
Output data type: ufix1
For VHDL, generates the bitwise AND operator operating on a set of individual slices
For Verilog, generates the reduce operator:
&a[lidx:ridx]
bitandreduce

bitcmp(a) Bitwise complement bitcmp

bitconcat(a, b)
bitconcat([a_vector])
bitconcat(a, b,c,d,...)
Concatenate fixed-point operands.
Operands can be of different signs.
Output data type: ufixN, where N is the sum of the word lengths of a and b.
For VHDL, generates the concatenation operator: (a & b)
For Verilog, generates the concatenation operator: {a , b}
bitconcat

bitget(a,idx)
Access a bit at position idx.
For VHDL, generates the slice operator: a(idx)
For Verilog, generates the slice operator: a[idx]
bitget

bitor(a, b) Bitwise OR bitor

bitorreduce(a, lidx, ridx)
Bitwise OR of a field of consecutive bits within a. The field is delimited by lidx and ridx.
Output data type: ufix1
For VHDL, generates the bitwise OR operator operating on a set of individual slices.
For Verilog, generates the reduce operator:
|a[lidx:ridx]
bitorreduce

bitset(a, idx, val)
Set or clear bit(s) at position idx.
If val = 0, clears the indicated bit(s). Otherwise, sets the indicated bits.
bitset

bitreplicate(a, n)
Concatenate bits of fi object a n times
bitreplicate

bitror(a, idx)
Rotate right.
idx must be a positive integer. The value of idx can be greater than the word length of a. idx is always normalized to mod(idx, wlen) , where wlen is the word length of a.
For VHDL, generates the ror operator.
For Verilog, generates the following expression (where wl is the word length of a:
a >> idx || a << wl - idx
bitror

bitset(a, idx, val)
Set or clear bit(s) at position idx.
If val = 0, clears the indicated bit(s). Otherwise, sets the indicated bits.
bitset

bitshift(a, idx)
Note: for efficient HDL code generation use, use bitsll, bitsrl, or bitsra instead of bitshift.
Shift left or right, based on the positive or negative integer value of‘idx.
idx must be an integer.
For positive values of idx, shift left idx bits.
For negative values of idx, shift right idx bits.
If idx is a variable, generated code contains logic for both left shift and right shift.
Result values saturate if the overflowMode of a is set to saturate.
bitshift

bitsliceget(a, lidx, ridx)
Access consecutive set of bits from lidx to ridx.
Output data type: ufixN, where N = lidx-ridix+1.
bitsliceget

bitsll(a, idx)
Shift left logical.
idx must be a scalar within the range
0 <= idx < wl
where wl is the word length of a.
Overflow and rounding modes of input operand a are ignored.
Generates sll operator in VHDL.
Generates << operator in Verilog.
bitsll

bitsra(a, idx)
Shift right arithmetic.
idx must be a scalar within the range
0 <= idx < wl
where wl is the word length of a,
Overflow and rounding modes of input operand a are ignored.
Generates sra operator in VHDL.
Generates >>> operator in Verilog.
bitsra

bitsrl(a, idx)
Shift right logical.
idx must be a scalar within the range
0 <= idx < wl
where wl is the word length of a.
Overflow and rounding modes of input operand a are ignored.
Generates srl operator in VHDL.
Generates >> operator in Verilog.
bitsrl

bitxor(a, b) Bitwise XOR bitxor

bitxorreduce(a, lidx, ridx)
Bitwise XOR reduction.
Bitwise XOR of a field of consecutive bits within a. The field is delimited by lidx and ridx.
Output data type: ufix1
For VHDL, generates a set of individual slices.
For Verilog, generates the reduce operator:
^a[lidx:ridx]
bitxorreduce

getlsb(a) Return value of LSB. getlsb

getmsb(a) Return value of MSB. getmsb

Embedded MATLAB Function Block Syntax	Description	See Also
`bitand(a, b)`	Bitwise AND	`bitand`
`bitandreduce(a, lidx, ridx)`	Bitwise AND of a field of consecutive bits within `a`. The field is delimited by `lidx` , `ridx`. Output data type: `ufix1` For VHDL, generates the bitwise AND operator operating on a set of individual slices For Verilog, generates the reduce operator: &a[lidx:ridx]	`bitandreduce`
`bitcmp(a)`	Bitwise complement	`bitcmp`
`bitconcat(a, b)` `bitconcat([a_vector])` `bitconcat(a, b,c,d,...)`	Concatenate fixed-point operands. Operands can be of different signs. Output data type: `ufixN`, where `N` is the sum of the word lengths of `a` and `b`. For VHDL, generates the concatenation operator: `(a & b)` For Verilog, generates the concatenation operator: `{a , b}`	`bitconcat`
`bitget(a,idx)`	Access a bit at position `idx`. For VHDL, generates the slice operator: `a(idx)` For Verilog, generates the slice operator: `a[idx]`	`bitget`
`bitor(a, b)`	Bitwise OR	`bitor`
`bitorreduce(a, lidx, ridx)`	Bitwise OR of a field of consecutive bits within `a`. The field is delimited by `lidx` and `ridx`. Output data type: `ufix1` For VHDL, generates the bitwise OR operator operating on a set of individual slices. For Verilog, generates the reduce operator: \|a[lidx:ridx]	`bitorreduce`
`bitset(a, idx, val)`	Set or clear bit(s) at position `idx`. If `val = 0`, clears the indicated bit(s). Otherwise, sets the indicated bits.	`bitset`
`bitreplicate(a, n)`	Concatenate bits of `fi` object `a` `n` times	`bitreplicate`
`bitror(a, idx)`	Rotate right. `idx` must be a positive integer. The value of `idx` can be greater than the word length of `a`. `idx` is always normalized to `mod(idx, wlen)` , where `wlen` is the word length of `a`. For VHDL, generates the `ror` operator. For Verilog, generates the following expression (where `wl` is the word length of `a`: a >> idx \|\| a << wl - idx	`bitror`
`bitset(a, idx, val)`	Set or clear bit(s) at position `idx`. If `val = 0`, clears the indicated bit(s). Otherwise, sets the indicated bits.	`bitset`
`bitshift(a, idx)`	Note: for efficient HDL code generation use, use `bitsll`, `bitsrl`, or `bitsra` instead of `bitshift`. Shift left or right, based on the positive or negative integer value of‘`idx`. `idx` must be an integer. For positive values of `idx`, shift left `idx` bits. For negative values of `idx`, shift right `idx` bits. If `idx` is a variable, generated code contains logic for both left shift and right shift. Result values saturate if the `overflowMode` of `a` is set to `saturate`.	`bitshift`
`bitsliceget(a, lidx, ridx)`	Access consecutive set of bits from `lidx` to `ridx`. Output data type: `ufixN`, where `N = lidx-ridix+1`.	`bitsliceget`
`bitsll(a, idx)`	Shift left logical. `idx` must be a scalar within the range 0 <= idx < wl where `wl` is the word length of `a`. Overflow and rounding modes of input operand `a` are ignored. Generates `sll` operator in VHDL. Generates `<<` operator in Verilog.	`bitsll`
`bitsra(a, idx)`	Shift right arithmetic. `idx` must be a scalar within the range 0 <= idx < wl where `wl` is the word length of `a`, Overflow and rounding modes of input operand `a` are ignored. Generates `sra` operator in VHDL. Generates `>>>` operator in Verilog.	`bitsra`
`bitsrl(a, idx)`	Shift right logical. `idx` must be a scalar within the range 0 <= idx < wl where `wl` is the word length of `a`. Overflow and rounding modes of input operand `a` are ignored. Generates `srl` operator in VHDL. Generates `>>` operator in Verilog.	`bitsrl`
`bitxor(a, b)`	Bitwise XOR	`bitxor`
`bitxorreduce(a, lidx, ridx)`	Bitwise XOR reduction. Bitwise XOR of a field of consecutive bits within `a`. The field is delimited by `lidx` and `ridx`. Output data type: `ufix1` For VHDL, generates a set of individual slices. For Verilog, generates the reduce operator: ^a[lidx:ridx]	`bitxorreduce`
`getlsb(a)`	Return value of LSB.	`getlsb`
`getmsb(a)`	Return value of MSB.	`getmsb`

Bit Slice and Bit Concatenation Functions

This section shows you how to use the Embedded MATLAB functions bitsliceget and bitconcat to access and manipulate bit slices (fields) in a fixed-point or integer word. As an example, consider the operation of swapping the upper and lower 4-bit nibbles of an 8-bit byte. The following example accomplishes this without resorting to traditional mask-and-shift techniques.

function y = fcn(u)
% NIBBLE SWAP 
y = bitconcat( …
      bitsliceget(u, 4, 1), 
      bitsliceget(u, 8, 5));

The bitsliceget and bitconcat functions map directly to slice and concat operators in both VHDL and Verilog.

The following listing shows the corresponding generated VHDL code.

ENTITY fcn IS
    PORT (
        clk : IN std_logic; 
        clk_enable : IN std_logic; 
        reset : IN std_logic;
        u : IN std_logic_vector(7 DOWNTO 0);
        y : OUT std_logic_vector(7 DOWNTO 0));
END nibble_swap_7b;


ARCHITECTURE fsm_SFHDL OF fcn IS


BEGIN
    -- NIBBLE SWAP
    y <= u(3 DOWNTO 0) & u(7 DOWNTO 4);
END fsm_SFHDL;

The following listing shows the corresponding generated Verilog code.

module fcn (clk, clk_enable, reset, u, y );
    input clk;
    input clk_enable;
    input reset;
    input [7:0] u;
    output [7:0] y;

    // NIBBLE SWAP
    assign y = {u[3:0], u[7:4]};

endmodule

Shift and Rotate Functions

The Embedded MATLAB Function block supports shift and rotate functions that mimic HDL-specific operators without saturation and rounding logic.

The following Embedded MATLAB code implements a barrel shifter/rotator that performs a selected operation (based on the mode argument) on a fixed point input operand.

function y   = fcn(u, mode)
% Multi Function Barrel Shifter/Rotator

% fixed width shift operation
fixed_width = uint8(3);

switch mode
    case 1
        % shift left logical
        y = bitsll(u, fixed_width);
    case 2
        % shift right logical
        y = bitsrl(u, fixed_width);
    case 3
        % shift right arithmetic
        y = bitsra(u, fixed_width);
    case 4
        % rotate left
        y = bitrol(u, fixed_width);
    case 5
        % rotate right
        y = bitror(u, fixed_width);
    otherwise
        % do nothing
        y = u;
end

In VHDL code generated for this function, the shift and rotate functions map directly to shift and rotate instructions in VHDL.

     CASE mode IS
            WHEN "00000001" =>
                -- shift left logical
                --'<S2>:1:8'
                cr := signed(u) sll 3;
                y <= std_logic_vector(cr);
            WHEN "00000010" =>
                -- shift right logical
                --'<S2>:1:11'
                b_cr := signed(u) srl 3;
                y <= std_logic_vector(b_cr);
            WHEN "00000011" =>
                -- shift right arithmetic
                --'<S2>:1:14'
                c_cr := SHIFT_RIGHT(signed(u) , 3);
                y <= std_logic_vector(c_cr);
            WHEN "00000100" =>
                -- rotate left
                --'<S2>:1:17'
                d_cr := signed(u) rol 3;
                y <= std_logic_vector(d_cr);
            WHEN "00000101" =>
                -- rotate right
                --'<S2>:1:20'
                e_cr := signed(u) ror 3;
                y <= std_logic_vector(e_cr);
            WHEN OTHERS => 
                -- do nothing
                --'<S2>:1:23'
                y <= u;
        END CASE;

The corresponding Verilog code is similar, except that Verilog does not have native operators for rotate instructions.

             case ( mode)
                1 :
                    begin
                        // shift left logical
                        //'<S2>:1:8'
                        cr = u <<< 3;
                        y = cr;
                    end
                2 :
                    begin
                        // shift right logical
                        //'<S2>:1:11'
                        b_cr = u >> 3;
                        y = b_cr;
                    end
                3 :
                    begin
                        // shift right arithmetic
                        //'<S2>:1:14'
                        c_cr = u >>> 3;
                        y = c_cr;
                    end
                4 :
                    begin
                        // rotate left
                        //'<S2>:1:17'
                        d_cr = {u[12:0], u[15:13]};
                        y = d_cr;
                    end
                5 :
                    begin
                        // rotate right
                        //'<S2>:1:20'
                        e_cr = {u[2:0], u[15:3]};
                        y = e_cr;
                    end
                default :
                    begin
                        // do nothing
                        //'<S2>:1:23'
                        y = u;
                    end
            endcase

Useful Embedded MATLAB Function Block Design Patterns for HDL

Using Complex Signals

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