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The RAM blocks let you:
Simulate the behavior of a single-port or dual-port RAM in your model.
Generate an interface to the inputs and outputs of the RAM in HDL code.
Generate RTL code that can be inferred as a RAM by most synthesis tools, for most FPGAs.
The RAM blocks are grouped together in the hdldemolib library, as shown in the following figure. The library provides three type of RAM blocks:
Dual Port RAM
Simple Dual Port RAM
Single Port RAM
To open the library, type the following command at the MATLAB prompt:
hdldemolib
Then, drag the desired RAM block from the hdldemolib library to your model, and set the block parameters and connect signals following the guidelines in the following sections.
The RAM-Based FIR Filter demo (hdlcoderfirram.mdl) provides an example of VHDL code generation for a Dual Port RAM block. Run this demo to acquaint yourself with the generated code.
The HDL device under test (DUT) in the model is the FIR_RAM subsystem. The FIR_RAM subsystem contains a Dual Port RAM block. The entity and architecture definitions generated for this block are written to DualPortRAM_Inst0.vhd .
The code generated for the top-level DUT, FIR_RAM.vhd, contains the component instantiation for the Dual Port RAM block.
The following figure shows the Dual Port RAM block.
The block has the following input and output ports:
wr_din : Data input. Only scalar signals can be connected to this port. The data type of the input signal can be fixed point, integer, or complex, and can be of any desired width. The port inherits the width and data type of its input signal.
wr_addr, rd_addr: Write and read address ports, respectively.
To set the width of the address ports, enter the desired width value (minimum width 2 bits, maximum width 16 bits ) into the Address port width field of the block GUI, as shown in the following figure. The default width is 8 bits.
The data type of signals connected to these ports must be unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0.
Vector signals are not accepted at the address ports.
wr_en: Write enable. This port must be connected to a Boolean signal.
wr_dout, rd_dout: Output ports with read data for addresses wr_addr and rd_addr, respectively.
Tip If data output at the write port is not required, you can achieve better RAM inference with synthesis tools by using the Simple Dual Port RAM block rather than the Dual Port RAM block. |
During a write, new data appears at the output of the write port (wr_dout) of the Dual Port RAM block. If a read operation is performed at the same address at the read port, old data is read at the output (rd_dout).
The following figure shows the Simple Dual Port RAM block.
This block is similar to the Dual Port RAM. It differs from Dual Port RAM in its read-during-write behavior, and it does not have the data output at the write port (wr_dout).
The block has the following input and output ports:
wr_din : Data input. Only scalar signals can be connected to this port. The data type of the input signal can be fixed point, integer, or complex, and can be of any desired width. The port inherits the width and data type of its input signal.
wr_addr, rd_addr: Write and read address ports, respectively.
To set the width of the address ports, enter the desired width value (minimum width 2 bits, maximum width 16 bits) into the Address port width field of the block GUI, as shown in the following figure. The default width is 8 bits.
The data type of signals connected to these ports must be unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0.
Vector signals are not accepted at the address ports.
wr_en: Write enable. This port must be connected to a Boolean signal.
rd_dout: Output port with read data for addresses wr_addr and rd_addr, respectively.
During a write operation, if a read operation is performed at the same address at the read port, old data is read at the output.
The following figure shows the Single Port RAM block.
The block has the following input and output ports:
din : Data input. Only scalar signals can be connected to this port. The data type of the input signal can be fixed point, integer, or complex, and can be of any desired width. The port inherits the width and data type of its input signal.
addr: Write address port.
To set the width of the address ports, enter the desired width value (minimum width 2 bits, maximum width 16 bits) into the Address port width field of the block GUI, as shown in the following figure. The default width is 8 bits.
The data type of signals connected to these ports must be unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0.
Vector signals are not accepted at the address ports.
we: Write enable. This port must be connected to a Boolean signal.
dout: Output port with data for address addr.
The Output data during write drop-down menu provides options that control how the RAM handles output/read data. These options are:
New data (default): During a write, new data appears at the output port (dout).
Old data: During a write, old data appears at the output port (dout).
Note Depending on your synthesis tool and target device, the setting of Output data during write may affect the result of RAM inference. See Limitations for RAM Blocks for further information on read-during-write behavior in hardware. |
The following general considerations apply to code generation for any of the RAM blocks:
Code generated for a RAM block is generated to a separate file in the target directory. The naming convention for this file is blockname.ext, where blockname is derived from the name assigned to the RAM block, and ext is the target language filename extension.
RAM blocks are implemented as subsystems, primarily for use in simulation. The coder generates a top-level interface (entity and RTL architecture) for the block; code is not generated for the underlying blocks. The generated interface is similar to the subsystem interface described in Generating a Black Box Interface for a Subsystem.
For all RAM blocks, data reads out from the output ports with a latency of 1 clock cycle.
The generated code for the RAM blocks does not include a reset signal. Generation of a reset is omitted because in the presence of a reset signal, synthesis tools would not infer a RAM from the HDL code.
Most synthesis tools will infer RAM from the generated HDL code. However, your synthesis tool may not map the generated code to RAM for the following reasons:
A small RAM size: your synthesis tool may implement a small RAM with registers for better performance.
The presence of a clock enable signal. It is possible to suppress generation of a clock enable signal Dual Port RAM and Single Port RAM blocks, as described in Limitations for RAM Blocks.
Take care to verify that your synthesis tool produces the expected result when synthesizing code generated for the Dual Port RAM block.
If data output at the write port is not required, you can achieve better RAM inferring with synthesis tools by using the Simple Dual Port RAM block rather than the Dual Port RAM block.
The following table shows HDL implementation names and implementation parameters for each type of RAM block..
| RAM Block | Implementation | Implementation Parameter |
|---|---|---|
| Dual Port RAM | hdldefaults. RamBlockDualHDLInstantiation | RAMStyle |
| Simple Dual Port RAM | hdldefaults. RamBlockSimpDualHDLInstantiation | RAMStyle |
| Single Port RAM | hdldefaults. RamBlockSingleHDLInstantiation | RAMStyle |
The RAMStyle implementation parameter lets you enable or suppress generation of clock enable logic. RAMStyle supports the following parameter values:
'default': This is the default value. Generates RAM structures using HDL templates that include a clock enable signal, and an empty RAM wrapper.
'generic': Generates RAM template without clock enable, and a RAM wrapper that implements the clock enable logic.
In many cases, you can use the default and leave RAMStyle unspecified. However, some synthesis tools do not support RAM inference with a clock enable. You may want to specify RAMStyle as 'generic' if your synthesis tool does not support RAM structures with a clock enable, and cannot map generated HDL code to FPGA RAM resources. To learn how to use generic style RAM for your design, see the Getting Started with RAM and ROM demo in Simulink demo. To open the demo, type the following command at the MATLAB prompt:
hdlcoderramrom
The following limitations apply to the use of RAM blocks in HDL code generation:
If you use RAM blocks to perform concurrent read and write operations, you should manually verify the read-during-write behavior in hardware. The read-during-write behavior of the RAM blocks in Simulink matches that of the generated behavioral HDL code. However, a synthesis tool may not follow the same behavior during RAM inferring, causing the read-during-write behavior in hardware to differ from the behavior of the Simulink model or generated HDL code. Actual read-during-write behavior in hardware depends on how synthesis tools infer RAM from generated HDL code, and on the hardware architecture of the target device.
The RAM blocks in the hdldemolib library implement RAM structures using HDL templates that include a clock enable signal.
However, some synthesis tools do not support RAM inference with a clock enable. As an alternative, the coder provides a generic style of HDL templates that do not use a clock enable signal for the RAM structures. The generic RAM template implements clock enable with logic in a wrapper around the RAM.
You may want to use the generic RAM style if your synthesis tool does not support RAM structures with a clock enable, and cannot map generated HDL code to FPGA RAM resources. To learn how to use generic style RAM for your design, see the Getting Started with RAM and ROM demo in Simulink demo. To open the demo, type the following command at the MATLAB prompt:
hdlcoderramrom
Simulink HDL Coder does not provide a ROM block, but you can easily build one using basic Simulink blocks. The new Getting Started with RAM and ROM in Simulink demo includes an example in which a ROM is built using a Lookup Table block and a Unit Delay block. To open the demo, type the following command at the MATLAB prompt:
hdlcoderramrom
 | Accessing the hdldemolib Library Blocks | HDL Counter |  |
Learn more about Simulink through this collection of videos, articles, technical literature and the Getting Started with Simulink Guide.
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