checkhdl - Check subsystem or model for HDL code generation compatibility

Syntax

checkhdl(bdroot) checkhdl(modelname) checkhdl(modelname/subsys) checkhdl(gcb) output = checkhdl(system)

Description

checkhdl(bdroot) examines the current model for HDL code generation compatibility and generates a compatibility report.

checkhdl generates an HTML HDL Code Generation Check Report, writes the report to the target folder, and displays the report in a browser window.

The report is in table format. Each entry in the table includes a hyperlink to a block or subsystem that caused a problem. When you click the hyperlink, the block of interest highlights and displays (if the model referenced by the report is open). If checkhdl finds no errors, the report contains only a hyperlink to the subsystem or model selected for code generation.

The report file naming convention is system_report.html, where system is the name of the subsystem or model passed in to checkhdl.

When a model or subsystem passes checkhdl without errors, that does not imply successful completion of code generation in all cases. checkhdl does not verify all block parameters.

checkhdl(modelname) examines the model explicitly specified by modelname for HDL code generation compatibility and generates a compatibility report.

checkhdl(modelname/subsys) examines a specified subsystem within the model specified by modelname for HDL code generation compatibility and generates a compatibility report. subsys specifies the name of the subsystem to check. subsys must be at the top (root) level of the current model. It cannot be a subsystem nested at a lower level of the model hierarchy.

checkhdl(gcb) examines the currently selected subsystem within the current model for HDL code generation compatibility and generates a compatibility report.

output = checkhdl(system)

where system specifies a model or subsystem in any of the forms described previously.

When the command includes an output argument, checkhdl does not generate a report. Instead, it returns a 1xN struct array with one entry for each error, warning, or message.

Use checkhdl to check your subsystems or models before generating HDL code. checkhdl reports three levels of compatibility problems:

Errors: Errors cause the code generation process to terminate. Fix all reported errors before generating HDL code again. A typical error would be the use of an unsupported data type.
Warnings: Warnings indicate problems in the generated code, but generally allow HDL code generation to continue. For example, the presence of an unsupported block in the model would raise a warning. In this case, the code generator attempts to proceed as if the block were not present in the design. This strategy could lead to errors later in the code generation process, which would then terminate.
Messages: Messages are indications that the HDL code generator treats some data types in a way that differs from thie usual treatment. For example, the coder automatically single-precision floating-point data types to double-precision because VHDL and Verilog do not support single-precision data types.

Examples

Check the subsystem symmetric_fir within the model sfir_fixed for HDL code generation compatibility and generate a compatibility report.

checkhdl('sfir_fixed/symmetric_fir')

Check the subsystem symmetric_fir_err within the model sfir_fixed_err for HDL code generation compatibility, and return information on problems encountered in the struct output.

output = checkhdl('sfir_fixed_err/symmetric_fir_err')
### Starting HDL Check.
...
### HDL Check Complete with 4 errors, warnings and messages.

The following MATLAB commands display the top-level structure of the struct output, and its first cell.

output = 

1x4 struct array with fields:
    path
    type
    message
    level


output(1)

ans = 

       path: 'sfir_fixed_err/symmetric_fir_err/Product'
       type: 'block'
    message: 'Unhandled mixed double and non-double datatypes at ports of block'
      level: 'Error'