HoldInputDataBetweenSamples - Specify how long subrate signal values are held in valid state
Settings
'on' (default)
Data values for subrate signals are held in a valid state across N base-rate
clock cycles, where N is the number of base-rate
clock cycles that elapse per subrate sample period. (N is >=
2.)
'off'
Data values for subrate signals are held in a valid state for
only one base-rate clock cycle. For the subsequent base-rate cycles,
data is in an unknown state (expressed as 'X')
until leading edge of the next subrate sample period.
Usage Notes
In most cases, the default ('on') is the
correct setting for this property. This setting matches the behavior
of a Simulink simulation, in which subrate signals are always
held valid through each base-rate clock period.
In some cases (for example modeling memory or memory interfaces),
it is desirable to set HoldInputDataBetweenSamples to 'off'.
In this way you can obtain diagnostic information about when data
is in an invalid ('X') state.
See Also
HoldTime, Generating HDL Code for Multirate Models
 | Highlightcolor | | HoldTime |  |
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