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makehdl(bdroot)
makehdl('modelname')
makehdl('modelname/subsys')
makehdl(gcb)
makehdl(bdroot, 'PropertyName', PropertyValue,...)
makehdl('modelname', 'PropertyName',
PropertyValue,...)
makehdl('modelname/subsys','PropertyName',PropertyValue,...)
makehdl(gcb, 'PropertyName', PropertyValue,...)
makehdl generates HDL RTL code (VHDL or Verilog) from a model or subsystem. We will refer to a model or subsystem from which code is generated as the device under test (DUT).
makehdl(bdroot) generates HDL code from the current model, using default values for all properties.
makehdl('modelname') generates HDL code from the model explicitly specified by 'modelname', using default values for all properties.
makehdl('modelname/subsys') generates HDL code from a subsystem within the model specified by 'modelname', using default values for all properties.
'subsys' specifies the name of the subsystem. In the current release, this must be a subsystem at the top (root) level of the current model; it cannot be a subsystem nested at a lower level of the model hierarchy.
makehdl(gcb) generates HDL code from the currently selected subsystem within the current model, using default values for all properties.
makehdl(bdroot, 'PropertyName', PropertyValue,...) generates HDL code from the current model, explicitly specifying one or more code generation options as property/value pairs.
makehdl('modelname', 'PropertyName', PropertyValue,...) generates HDL code from the model explicitly specified by 'modelname', explicitly specifying one or more code generation options as property/value pairs.
makehdl('modelname/subsys','PropertyName',PropertyValue,...) generates HDL code from a subsystem within the model specified by 'modelname', explicitly specifying one or more code generation options as property/value pairs.
'subsys' specifies the name of the subsystem. In the current release, this must be a subsystem at the top (root) level of the current model; it cannot be a subsystem nested at a lower level of the model hierarchy.
makehdl(gcb, 'PropertyName', PropertyValue,...) generates HDL code from the currently selected subsystem within the current model, explicitly specifying one or more code generation options as property/value pairs.
Property/value pairs are passed in the form
'PropertyName', PropertyValue
These property settings determine characteristics of the generated code, such as HDL element naming and whether certain optimizations are applied. The next section, HDL Code Generation Defaults, summarizes the default actions of the code generator.
For detailed descriptions of each property and its effect on generated code, see Properties — Alphabetical List, and Property Reference.
This section summarizes the default actions of the code generator. Most defaults can be overridden by passing in appropriate property/value settings to makehdl. Properties — Alphabetical List describes all makehdl properties in detail.
The TargetLanguage property determines whether VHDL or Verilog code is generated. The default is VHDL.
makehdl writes generated files to hdlsrc, a subdirectory of the current working directory. This directory is called the target directory. makehdl creates a target directory if it does not already exist.
makehdl generates separate HDL source files for the DUT and each subsystem within it. In addition, makehdl generates script files for HDL simulation and synthesis tools. File names derive from the name of the DUT. File names are assigned by the coder and are not user-assignable. The following table summarizes file-naming conventions.
| File | Name | |
|---|---|---|
| Verilog source code | system.v, where system is the name of the DUT. | |
| VHDL source code | system.vhd, where system is the name of the DUT. | |
| Timing controller code | Timing_Controller.vhd (VHDL) or Timing_Controller.v (Verilog). This file contains a module defining timing signals (clock, reset, external clock enable inputs and clock enable output) in a separate entity or module. Timing controller code is generated if required by the design; a purely combinatorial model does not generate timing controller code. | |
| Mentor Graphics ModelSim compilation script | system_compile.do, where system is the name of the DUT. | |
| Synplify synthesis script | system_synplify.tcl, where system is the name of the DUT. | |
| VHDL package file | system_pkg.vhd, where system is the name of the DUT. A package file is generated only if the design requires a VHDL package. | |
| Mapping file | system_map.txt, where system is the name of the DUT. This report file maps generated entities (or modules) to the subsystems that generated them. See Code Tracing Using the Mapping File. |
Unique names are assigned to generated VHDL entities or Verilog modules. Entity or module names are derived from the names of the DUT. Name conflicts are resolved by the use of a postfix string.
HDL port names are assigned according to the following conventions:
| HDL Port | Name |
|---|---|
| Input | Same as corresponding port name on the DUT (name conflicts resolved according to rules of the target language) |
| Output | Same as corresponding port name on the DUT (name conflicts resolved according to rules of the target language) |
| Clock input | clk |
| Clock enable input | clk_enable |
| Clock enable output | ce_out |
| Reset input | reset |
HDL port directions and data types
Port direction: IN or OUT, corresponding to the port on the DUT.
Clock, clock enable, and reset port data types: VHDL type STD_LOGIC_VECTOR or Verilog type wire.
Input and output port data types: VHDL type STD_LOGIC_VECTOR or Verilog type wire. Port widths are determined by the model.
HDL signal names and data types:
HDL signals generated from named signals in the model retain their signal names.
For unnamed signals in the model, HDL signal names are derived from the concatenated names of the block and port connected to the signal in the DUT: blockname_portname. Conflicting names are made unique according to VHDL or Verilog rules.
Signal data types are determined by the data type of the corresponding signal in the model. Each signal declaration is annotated with a comment indicating the data type.
VHDL-specific defaults:
Generated VHDL files include both entity and architecture code.
VHDL configurations are placed in any file that instantiates a component.
VHDL code checks for rising edges via the logic IF clock'event AND clock='1' THEN... , when operating on registers.
When creating labels for VHDL GENERATE statements, makehdl appends _gen to section and block names. makehdl names output assignment block labels with the string outputgen.
A type-safe representation is used for concatenated zeros: '0' & '0'...
Generated code for registers uses asynchronous reset logic with an active-high (1) reset level.
The postfix string _process is appended to process names.
On Microsoft® Windows® platforms, carriage return/linefeed (CRLF) character sequences are never emitted in generated code.
In general, generated HDL code produces results that are bit-true and cycle-accurate with respect to the original model (that is, the HDL code exactly reproduces simulation results from the model).
However, some block implementations generate code that includes certain block-specific performance and area optimizations. These optimizations can produce numeric results or timing differences that differ from those produced by the original model (see Generating Bit-True Cycle-Accurate Models).
The following call to makehdl generates Verilog code for the subsystem symmetric_fir within the model sfir_fixed.
makehdl('sfir_fixed/symmetric_fir','TargetLanguage', 'Verilog')
The following call to makehdl generates VHDL code for the current model. Code is generated into the target directory hdlsrc, with all code generation options set to default values.
makehdl(bdroot)
The following call to makehdl directs the HDL compatibility checker (see checkhdl) to check the subsystem symmetric_fir within the model sfir_fixed before code generation starts. If no compatibility errors are encountered, makehdl generates VHDL code for the subsystem symmetric_fir. Code is generated into the target directory hdlsrc, with all code generation options set to default values.
makehdl('sfir_fixed/symmetric_fir','CheckHDL','on') | hdlsetup | makehdltb |  |
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