| Simulink® HDL Coder™ | |
makehdltb('modelname/subsys')
makehdltb('modelname/subsys', 'PropertyName',
PropertyValue,...)
makehdltb('modelname/subsys') generates an HDL test bench from the specified subsystem within a model, using default values for all properties. The modelname/subsys argument gives the path to the subsystem under test. This subsystem must be at the top (root) level of the current model. The generated test bench is designed to interface to and validate HDL code generated from subsys (or from a subsystem with a functionally identical public interface).
A typical practice is to generate HDL code for a subsystem, followed immediately by generation of a test bench to validate the same subsystem (see Examples).
Note If makehdl has not previously executed successfully within the current session, makehdltb generates model code before generating the test bench code. Test bench code and model code must both be generated in the same target language. If the target language specified for makehdltb differs from the target language specified for the previous makehdl execution, makehdltb will regenerate model code in the same language specified for the test bench. Properties passed in to makehdl persist after makehdl executes, and (unless explicitly overridden) will be passed in to subsequent makehdltb calls during the same session. |
makehdltb('modelname/subsys', 'PropertyName', PropertyValue,...) generates an HDL test bench from the specified subsystem within a model, explicitly specifying one or more code generation options as property/value pairs.
Property/value pairs are passed in the form
'PropertyName', PropertyValue
These property settings determine characteristics of the test bench code. Many of these properties are identical to those for makehdl, while others are specific to test bench generation (for example, options for generation of test bench stimuli). The next section, Defaults for Test Bench Code Generation, summarizes the defaults that are specific to generated test bench code.
For detailed descriptions of each property and its effect on generated code, see Properties — Alphabetical List, and Property Reference.
makehdltb generates test data from signals connected to inputs of the subsystem under test. Sample values for each stimulus signal are computed and stored for each time step of the simulation. The signal data is represented as arrays in the generated test bench code.
To help you validate generated HDL code, makehdltb also generates output data from signals connected to outputs of the subsystem under test. Like input data, sample values for each output signal are computed and stored for each time step of the simulation. The signal data is represented as arrays in the generated test bench code.
The total simulation time (set by the model's Stop Time parameter) determines the size of the stimulus and output data arrays. Computation of sample values can be time-consuming. Consider speeding up generation of signal data by entering a shorter Stop Time.
This section describes defaults that apply specifically to generation of test bench code. makehdltb has many properties and defaults in common with makehdl. See HDL Code Generation Defaults for a summary of these common properties and defaults.
By default, makehdltb generates an HDL source file containing test bench code and arrays of stimulus and output data. In addition, makehdltb generates script files that let you execute a simulation of the test bench and the HDL entity under test. Generated test bench file names (like makehdl generated file names) are based on the name of the DUT. The following table summarizes the default test bench file-naming conventions.
| File | Name | |
|---|---|---|
| Verilog test bench | system_tb.v, where system is the name of the system under test | |
| VHDL test bench | system_tb.vhd, where system is the name of the system under test | |
| Mentor Graphics ModelSim compilation script | system_tb_compile.do, where system is the name of the DUT | |
| Mentor Graphics ModelSim simulation script | system_tb_sim.do, where system is the name of the DUT |
The test bench forces clock, clock enable, and reset input signals.
The test bench forces clock enable and reset input to active high (1).
The clock input signal is driven high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.
The test bench forces reset signals.
The test bench applies a hold time of 2 nanoseconds to reset and data input signals.
In the following example, makehdl generates VHDL code for the subsystem symmetric_fir. After the coder indicates successful completion of code generation, makehdltb generates a VHDL test bench for the same subsystem.
makehdl('sfir_fixed/symmetric_fir')
### Applying HDL Code Generation Control Statements
### Begin VHDL Code Generation
### Working on sfir_fixed/symmetric_fir as hdlsrc\symmetric_fir.vhd
### HDL Code Generation Complete.
makehdltb('sfir_fixed/symmetric_fir')
### Begin TestBench Generation
### Generating Test bench: hdlsrc\symmetric_fir_tb.vhd
### Please wait ...
### HDL TestBench Generation Complete.
| makehdl |
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