Version 1.2 (R2007b) Simulink HDL Coder Software

This table summarizes what's new in V1.2 (R2007b):

New Features and Changes	Version Compatibility Considerations	Fixed Bugs and Known Problems	Related Documentation at Web Site
Yes Details below	Yes—Details labeled as Compatibility Considerations, below. See also Summary.	Bug Reports	No

New features and changes introduced in this version are:

• HDL Code Generation for Single-Clock Multirate Models

• Additional Blocks Supported for HDL Code Generation

• Dual Port RAM Block Supported for Simulation and Code Generation

• Block Implementation Parameters Include Output Pipelining

• Summary of GUI Updates

• Digital Filter Block Restriction Removed

• Support for New Embedded MATLAB Bitwise Functions

• Default Hardware Target for Synthesis Scripts Updated to Virtex-4

HDL Code Generation for Single-Clock Multirate Models

The coder now supports HDL code generation for single-clock, single-tasking multirate models. Your model can include blocks running at multiple sample rates:

• Within in the device under test (DUT)

• In the test bench driving the DUT

• In both the test bench and the DUT

Multirate code generation support is described in detail in Generating HDL Code for Multirate Models in the documentation.

Additional Blocks Supported for Multirate Code Generation

The following blocks, frequently used in construction of multirate models, are now supported for HDL code generation:

• Signal Attributes/Rate Transition

• Signal Processing Blockset/Signal Operations/Downsample

• Signal Processing Blockset/Signal Operations/Upsample

New Property Added in Support of Multirate Code Generation

To support multirate code generation, a new makehdl property, HoldInputDataBetweenSamples, has been added. This property determines how long (in terms of base rate clock cycles) data values for subrate signals are held in a valid state. See HoldInputDataBetweenSamples for details.

Requirements and Restrictions for Multirate Code Generation

Certain requirements and restrictions apply to the use of multirate models for HDL code generation. See Configuring Multirate Models for HDL Code Generation for further information.

Additional Blocks Supported for HDL Code Generation

The coder now supports the following blocks for HDL code generation:

• Additional Math & Discrete/Additional Discrete/Unit Delay Enabled

• Math Operations/Divide

• Math Operations/Math Function (sqrt function only)

• Signal Attributes/Rate Transition

• Signal Processing Blockset/Signal Operations/Downsample

• Signal Processing Blockset/Signal Operations/Upsample

• Dual Port RAM (For information on this new block, see also Dual Port RAM Block Supported for Simulation and Code Generation.)

See Summary of Block Implementations for a complete listing of blocks that are currently supported for HDL code generation.

Dual Port RAM Block Supported for Simulation and Code Generation

The coder now provides the Dual Port RAM Block for use in simulation and code generation.

The Dual Port RAM block lets you:

• Simulate the behavior of a dual-port RAM with registered outputs in your model.

• Generate an interface to the inputs and outputs of the RAM in HDL code.

See RAM Blocks for full details.

Block Implementation Parameters Include Output Pipelining

The coder now supports block implementation parameters, which let you control details of the code generated for specific block implementations. Block implementation parameters are passed as property/value pairs to forEach or forAll calls in a code generation control file.

Supported Block Implementation Parameters

Block implementation parameters supported in the current release include:

• 'OutputPipeline', nStages: This parameter lets you specify a pipelined implementation for selected blocks. The parameter value (nStages) specifies the number of pipeline stages (pipeline depth) in the generated code. OutputPipeline is supported by most Simulink HDL Coder HDL Coder block implementations.

• Interface generation parameters let you customize features of an interface generated for the following block types:

  • simulink/Ports & Subsystems/Model

  • built-in/Subsystem

  • lfilinklib/HDL Cosimulation

  • modelsimlib/HDL Cosimulation

  For example, you can specify generation of a black box interface for a subsystem, and pass in parameters that specify the generation and naming of clock, reset, and other ports in HDL code. Interface generation parameters are described in Customizing the Generated Interface.

For more information on block implementation parameters, see the following sections in the documentation:

• Specifying Block Implementations and Parameters in the Control File

• Block Implementation Parameters

• Summary of Block Implementations

Using hdlnewforeach to Find Block Implementation Parameters

Given a selection of one or more blocks from your model, the hdlnewforeach function returns information about the available HDL implementations for each block.

In the current release, the information returned by hdlnewforeach has been expanded. hdlnewforeach now returns an optional cell array of strings specifying the parameter(s) corresponding to each block implementation.

See Generating Selection/Action Statements with the hdlnewforeach Function for details.

Summary of GUI Updates

The following updates have been made to the Simulink HDL Coder GUI:

• The Enable prefix option is now supported by the GUI as well as by the EnablePrefix command-line property. See Enable prefix for details on this option.

  

• The default value for the Synthesis termination field of the EDA Tool Scripts dialog box has changed, as shown in the following figure. The default hardware target string in generated synthesis scripts now specifies

  • technology option: VIRTEX4

    In previous releases, this option defaulted to VIRTEX2.

  • part option: XC4VSX35

    In previous releases, this option defaulted to XC2V500.

  

  See also Default Hardware Target for Synthesis Scripts Updated to Virtex-4 .

Digital Filter Block Restriction Removed

In previous releases, Filter Design HDL Coder™ software was required to generate HDL code for the Digital Filter block when the Dialog parameters option was selected in the Coefficient source option group. This requirement has been removed.

In the current release, the HDL code generation requirements for the Digital Filter block vary according to the Coefficient source option you select, as follows:

• Dialog parameters: No additional toolboxes or blocksets required for HDL code generation.

• Discrete-time filter object: Filter Design HDL Coder software required.

• Input port(s): This option is not supported for HDL code generation.

Support for New Embedded MATLAB Bitwise Functions

The code supports the new Embedded MATLAB fixed-point bitwise functions introduced in R2007b. Many of these functions map directly to HDL bitwise operators, resulting in very efficient HDL code. See Using Fixed-Point Bitwise Functions for examples of the use of these functions in HDL code generation.

For general information on Embedded MATLAB bitwise functions, see Bitwise Operations in the Fixed-Point Toolbox documentation.

Compatibility Considerations

In previous releases, the return type of the bitget function was ufix8. For more efficient HDL code generation, the return data type of the bitget function has been changed to ufix1. If your existing Embedded MATLAB code performs type casts to adapt values returned from bitget for HDL code generation, you may be able to eliminate these type casts.

Default Hardware Target for Synthesis Scripts Updated to Virtex-4

The default hardware target string in generated synthesis scripts now specifies

• technology option: VIRTEX4

  In previous releases, this option defaulted to VIRTEX2.

• part option: XC4VSX35

  In previous releases, this option defaulted to XC2V500.

These updates affect the default value for the HDLSynthTerm property. The default is:

 ['set_option -technology VIRTEX4\n',...
 'set_option -part XC4VSX35\n',...
 'set_option -synthesis_onoff_pragma 0\n',...
 'set_option -frequency auto\n',...
 'project -run synthesis\n']

The default value for the HDLSynthTerm property appears in the Synthesis termination field of the EDA Tool Scripts dialog box, as shown in the following figure.

See also Generating Scripts for HDL Simulators and Synthesis Tools.

Compatibility Considerations

If you have existing models that generate synthesis scripts using the previous defaults for technology or part, you may want to update your models and regenerate scripts.

Version 1.3 (R2008a) Simulink HDL Coder Software

Version 1.1 (R2007a) Simulink HDL Coder Software

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