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Version 1.6 (R2009b) Simulink HDL Coder Software

This table summarizes what's new in Version 1.6 (R2009b):

New Features and ChangesVersion Compatibility ConsiderationsFixed Bugs and Known ProblemsRelated Documentation at Web Site
Yes
Details below
Yes—Details labeled as Compatibility Considerations, below. See also Summary.
None

Printable Release Notes: PDF

Current product documentation

New features and changes introduced in this version are:

Triggered Subsystems Support for HDL Code Generation

The coder now supports HDL code generation for triggered subsystems. See Code Generation for Enabled and Triggered Subsystems in the Simulink® HDL Coder™ documentation for further information.

Stateflow Events Support for HDL Code Generation

The coder now supports a single input event and unlimited output events in Stateflow® charts. for further information, see Using Input and Output Events in the Simulink HDL Coder documentation.

Support for Global Oversampling Clock

You can now generate global clock logic that allows you to integrate your DUT into a larger system easily, without using Upsample or Downsample blocks.

To generate global clock logic, you specify an oversampling factor. The oversampling factor expresses the desired rate of the global oversampling clock as a multiple of the base rate of the model. When you specify an oversampling factor, the coder generates the global oversampling clock. Then, it derives the required timing signals from the clock signal. Generation of the global oversampling clock affects only generated HDL code. The clock does not affect the simulation behavior of your model.

You can specify the desired factor as the Oversampling factor option in the Clock settings section of the Global Settings pane of the Configuration Parameters dialog . The following figure shows the option. Alsternatively, you can set the command-line property 'Oversampling'.

See Generating a Global Oversampling Clock in the Simulink HDL Coder documentation for further information.

Test Bench GUI Reorganized

The new Testbench generation output section of the GUI contains three new options:

To configure test bench options and generate test bench code, select one or more of the options of the Testbench generation output section. If you deselect all three options of the Testbench generation output section, the coder disables all options in the Configuration section of the Test Bench pane.

MATLAB Editor Supports VHDL and Verilog Syntax Highlighting

The MATLAB Editor now supports syntax highlighting for VHDL and Verilog code. See Highlighting Syntax to Help Ensure Correct Entries in the MATLAB documentation for further information on syntax highlighting.

Hyperlinked Requirements Comments Included in HTML Code Generation Reports

The coder now renders requirements comments as hyperlinked comments within generated HTML code generation reports. See Requirements Comments and Hyperlinks in the Simulink HDL Coder documentation for further information.

HTML Code Generation Report from Root-Level Model Supported

In previous releases, the coder did not support generation of HTML code generation reports from the root-level model. R2009b removes this restriction. You can now generate reports for the root-level model as well as for subsystems, blocks, Stateflow charts, or Embedded MATLAB™ blocks.

Generation of Simulink Model for Cosimulation of Generated HDL Code

The coder now supports generation of a Simulink model configured for:

The generated model includes a behavioral model of your design and a corresponding HDL Cosimulation block, configured to cosimulate the design using EDA Simulator Link™. You can generate an HDL Cosimulation block for either of the following:

See Generating a Simulink Model for Cosimulation with an HDL Simulator for further information.

Additional Simulink Blocks Supported for HDL Code Generation

The coder now supports the blocks listed in the following table for HDL code generation.

BlockImplementation

hdldemolib/HDL Streaming FFT

hdldefaults.FFT

Ports & Subsystems/Trigger

hdldefaults.TriggerPort

simulink/Discrete/Discrete FIR Filter

 hdldefaults.DiscreteFIRFilterHDLInstantiation

simulink/Lookup Tables/Direct Lookup Table (n-D)

hdldefaults.DirectLookupTable

simulink/Lookup Tables/Lookup Table (n-D)

hdldefaults.LookupTableND

simulink/Lookup Tables/Prelookup

hdldefaults.PreLookup

Summary of Block Implementations in the Simulink HDL Coder documentation gives a complete listing of blocks that the coder supports for HDL code generation.

New hdldemolib Block Supports Streaming FFT

The new hdldemolib/HDL Streaming FFT block supports a Radix-2 DIF streaming FFT algorithm.

See HDL Streaming FFT in the Simulink HDL Coder documentation for details.

Algebraic Loops Disallowed for HDL Code Generation

The coder now checks for algebraic loops during the compatibility checking phase of the code generation process. If makehdl detects an algebraic loop inside the DUT, the coder displays an error message and ends the code generation process.

Compatibility Considerations

Restructure any of your models that contain algebraic loops such that algebraic loops do not occur. It is also good practice to set the Algebraic loop diagnostic in the Diagnostics pane of the Configuration Parameters dialog box to error.

DUT Argument Required for checkhdl and makehdl Commands

R2009b requires that calls to the following functions must specify the device under test (DUT):

When you call checkhdl or makehdl, specify the DUT as the initial argument to these functions, as in the following example:

makehdl('sfir_fixed/symmetric_fir','TargetLanguage', 'Verilog');

As in previous releases, you can specify the DUT in any of the following forms:

This requirement avoids certain ambiguities that occurred in calls to checkhdl or makehdl that did not pass in an explicit DUT argument.

In R2009b, the coder displays a warning if it encounters a call to checkhdl or makehdl without the DUT argument. In future releases, the coder will generate an error if it encounters a call to either of these functions without the DUT argument.

See also the checkhdl and makehdl function reference pages in the Simulink HDL Coder documentation.

Compatibility Considerations

If your M-files contain any calls to checkhdl or makehdl that do not specify the DUT, modify them to pass in the DUT as the initial argument.

AddClockEnablePort Implementation Parameter for RAM Blocks Deprecated

The AddClockEnablePort implementation parameter for the Dual Port RAM and Single Port RAM blocks is deprecated. The coder issues an error message if it detects a reference to AddClockEnablePort in a control file.

Compatibility Considerations

If you use the AddClockEnablePort in a control file to suppress to generation of a clock enable signal for RAM blocks:

To learn how to use generic style RAM for your design, see the new Getting Started with RAM and ROM in Simulink demo. To open the demo, type the following command at the MATLAB prompt:

hdlcoderramrom

Additional Lookup Table Blocks Supported

The coder now supports the following lookup table (LUT) blocks for HDL code generation:

Expanded LUT functionality supported for these blocks includes:

See Using Lookup Table Blocks in the Simulink HDL Coder documentation for details.

Discrete FIR Filter Supports Distributed Arithmetic Architecture

The code now supports distributed arithmetic (DA) filter implementations for the Discrete FIR Filter block. See Distributed Arithmetic Implementation Parameters for Digital Filter Blocks in the Simulink HDL Coder documentation for details.

Generation of Multicycle Path Constraint Information

The coder now supports generation of a text file that reports multicycle path constraint information. You can use this information with your synthesis tool.

To generate the file, select the Generate multicycle path information option in the EDA Tool Scripts pane of the Configuration Parameters dialog box. The following figure shows this option.

To generate a multicycle path constraint information file at the command line, set the MulticyclePathInfo property as shown in the following example.

makehdl(gcb,'MulticyclePathInfo', 'on');

See Generating Multicycle Path Information Files in the Simulink HDL Coder documentation for detailed information.

Biquad Filter and Digital Filter Blocks Support Complex Input Data and Coefficients

The Biquad Filter and Digital Filter blocks now support complex input data and coefficients for all filter structures except decimators and interpolators.

Support for Adding or Removing HDL Configuration Component

The HDL Coder submenu of the Tools menu now supports addition or removal of the HDL Coder configuration component of a model. The following figure shows the Remove HDL Configuration to Model option.

See Adding and Removing the HDL Configuration Component Simulink HDL Coder documentation for more information.

  

Simulink HDL Coder Release NotesSimulink HDL Coder Release Notes Version 1.5 (R2009a) Simulink HDL Coder SoftwareVersion 1.5 (R2009a) Simulink HDL Coder Software

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