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| Documentation → Simulink HDL Coder |
| Contents | Index |
This table summarizes what's new in Version 1.5 (R2009a):
| New Features and Changes | Version Compatibility Considerations | Fixed Bugs and Known Problems | Related Documentation at Web Site |
|---|---|---|---|
| Yes Details below | Yes—Details labeled as Compatibility
Considerations, below. See also Summary. | None | Printable Release Notes: PDF |
New features and changes introduced in this version are:
Additional Simulink Blocks Supported for HDL Code Generation
Distributed Arithmetic Implementations for the Digital Filter Block
Restriction on fi and fimath Rounding Modes in Embedded MATLAB Function Block Removed
Restriction on for Loop Increment in Embedded MATLAB Function Block Removed
Generic RAM Template Supports RAM Without a Clock Enable Signal
The hdlsupported.mdl block library has been reorganized into several sublibraries to help you locate the HDL-compatible blocks you need more easily. The following figure shows the top-level view of the hdlsupported.mdl library.
The set of supported blocks will change in future releases of the coder. To keep the hdlsupported.mdl current, you should rebuild the library each time you install a new release. See Supported Blocks Library in the Simulink HDL Coder documentation for further information.
To help you navigate more easily between generated code and your source model, the coder provides a traceability option that lets you generate reports from either the GUI or the command line. When you enable traceability, the coder creates and displays an HTML code generation report during the code generation process. The following figure shows the top-level page of a typical report.
The report comprises several sections:
The Summary section lists version and date information.
The Generated Source Files table contains hyperlinks to that let you view generated HDL code in a MATLAB Web browser window. This view of the code includes hyperlinks that let you view the blocks or subsystems from which the code was generated. You can click the names of source code files generated from your model to view their contents in a MATLAB Web browser window. The report supports two types of linkage between the model and generated code:
Code-to-model hyperlinks within the displayed source code let you view the blocks or subsystems from which the code was generated. Click on the hyperlinks to view the relevant blocks or subsystems in a Simulink model window.
Model-to-code linkage lets you view the generated code for any block in the model. To highlight a block's generated code in the HTML report, right-click the block and select HDL Coder > Navigate to Code from the context menu.
The Traceability Report allows you to account for Eliminated / Virtual Blocks that are untraceable, versus the listed Traceable Simulink Blocks / Stateflow Objects / Embedded MATLAB Scripts, providing a complete mapping between model elements and code.
To enable generation of the HTML code generation report, select Generate traceability report in the HDL Coder pane of the Configuration Parameters dialog box, as shown in the following figure.
See Creating and Using a Code Generation Report in the Simulink HDL Coder documentation for further information.
The coder now supports the blocks listed in the following table for HDL code generation.
| Block | Implementation(s) |
|---|---|
simulink/Additional Math & Discrete/ | hdldefaults.IncrementOrDecrementRWV |
simulink/Additional Math & Discrete/ | hdldefaults.IncrementOrDecrementRWV |
simulink/Additional Math & Discrete/ | hdldefaults.IncrementOrDecrementSI |
simulink/Additional Math & Discrete/ | hdldefaults.IncrementOrDecrementSI |
simulink/Discontinuties/Saturation Dynamic | hldefaults.SaturationDynamic |
Signal Routing/Go To | hdldefaults.GotoBlock |
Signal Routing/From | hdldefaults.FromBlock |
dsparch4/Biquad Filter | hdldefaults.BiquadFilterHDLInstantiation |
Ports & Subsystems/Enable | hdldefaults.EnablePort |
See Summary of Block Implementations in the Simulink HDL Coder documentation for a complete listing of blocks that are currently supported for HDL code generation.
The code now supports code generation for enabled subsystems, provided that they are configured as described in Code Generation for Enabled and Triggered Subsystems in the Simulink HDL Coder documentation.
The default HDL implementations for certain blocks has been changed. The following table lists these blocks, as well as their new default implementations and previous default implementations. All listed implementation classes belong to the package hdldefaults.
| Block | Default
Implementation Before R2009a | New Default Implementation |
|---|---|---|
simulink/Commonly Used Blocks/Constant simulink/Commonly Used Blocks/Ground dspsrcs4/DSP Constant | ConstantHDLEmission | Constant |
simulink/Commonly Used Blocks/Demux | DemuxHDLEmission | Demux |
simulink/Commonly Used Blocks/Mux | MuxHDLEmission | Mux |
simulink/Commonly Used Blocks/Switch | SwitchHDLEmission | SwitchRTW |
simulink/Math Operations/Complex to Real-Imag | ComplexToRealImagHDLEmission | ComplexToRealImag |
simulink/Math Operations/Real-Imag to Complex | RealImagtoComplexHDLEmission | RealImagtoComplex |
See Summary of Block Implementations in the Simulink HDL Coder documentation for a complete listing of blocks that are currently supported for HDL code generation.
If your models use default HDL block implementations for the affected blocks, the coder now defaults to the new implementations. The new implementations are compatible with the previous implementations and will produce identical results.
The older implementations for the listed blocks will be supported for a limited number of future releases. If your control files explicitly reference the previous default implementation for any of the affected blocks, the coder will continue to use the referenced implementation. You should consider removing or changing such references in your control files to use the new implementations.
A number of HDL block implementations have been changed. The following table lists these blocks, as well as their new implementations and the earlier implementations that they replace. All listed implementation classes belong to the package hdldefaults.
| Block | Implementation Before R2009a | New Implementation |
|---|---|---|
simulink/Math Operations/MinMax dspstat3/Maximum dspstat3/Minimum | MinMaxCascadeHDLEmission | MinMaxCascade |
simulink/Commonly Used Blocks/Sum simulink/Math Operations/Sum of Elements | SumTreeHDLEmission | SumTree |
simulink/Commonly Used Blocks/Product simulink/Math Operations/Product of Elements | ProductTreeHDLEmission | ProductTree |
simulink/Commonly Used Blocks/Sum simulink/Math Operations/Sum of Elements | SumCascadeHDLEmission | SumCascade |
simulink/Commonly Used Blocks/Product simulink/Math Operations/Product of Elements | ProductCascadeHDLEmission | ProductCascade |
See Summary of Block Implementations in the Simulink HDL Coder documentation for a complete listing of blocks that are currently supported for HDL code generation.
The new implementations are compatible with the previous implementations and will produce identical results.
The older implementations for the listed blocks will be supported for a limited number of future releases. If your control files explicitly reference the previous implementation for any of the affected blocks, the coder will continue to use the referenced implementation. You should consider removing or changing such references in your control files to use the new implementations.
Distributed Arithmetic (DA) is a widely used technique for implementing sum-of-products computations without using multipliers. DA distributes multiply and accumulate operations across shifters, lookup tables (LUTs) and adders in such a way that conventional multipliers are not required. The coder now supports DA implementations for the following FIR structures of the Digital Filter block:
dfilt.dffir
dfilt.dfsymfir
dfilt.dfasymdir
See Block Implementation Parameters in the Simulink HDL Coder documentation for further information.
The coder supports complex coefficients and complex input signals for fully parallel FIR and CIC filter structures of the Digital Filter block. In many cases, you can use complex data and complex coefficients in combination. The following table shows the filter structures that support complex data and/or coefficients, and the permitted combinations.
| Filter Structure | Complex Data | Complex Coefficients | Both Complex
Data and Coefficients |
|---|---|---|---|
| dfilt.dffir | Y | Y | Y |
| dfilt.dfsymfir | Y | Y | Y |
| dfilt.dfasymfir | Y | Y | Y |
| dfilt.dffirt | Y | Y | Y |
| mfilt.cicdecim | Y | N/A | N/A |
| mfilt.cicinterp | Y | N/A | N/A |
| mfilt.firdecim | Y | Y | N |
| mfilt.firinterp | Y | Y | N |
See Blocks That Support Complex Data for further information on how the coder supports use of complex data.
Requirements that you assign to Simulink blocks are now automatically included as comments in generated code. See the Simulink Verification and Validation User's Guide in the Simulink HDL Coder documentation for further information on requirements comments.
In previous releases, the coder did not support the convergent and round modes for the fi and fimath functions in Embedded MATLAB Function blocks.
This restriction has been removed; the coder now supports all fi and fimath rounding modes.
See also Generating HDL Code with the Embedded MATLAB Function Block in the Simulink HDL Coder documentation.
In previous releases, the use of for loops with an increment other than 1 in an Embedded MATLAB Function Block was not supported for HDL code generation.
This restriction has been removed. The coder now allows use of any increment in a for loop in an Embedded MATLAB Function Block.
See also Generating HDL Code with the Embedded MATLAB Function Block in the Simulink HDL Coder documentation.
The hdldemolib library provides three type of RAM blocks:
Dual Port RAM
Simple Dual Port RAM
Single Port RAM
These blocks (see RAM Blocks in the Simulink HDL Coder documentation) implement RAM structures using HDL templates that include a clock enable signal.
However, some synthesis tools do not support RAM inference with a clock enable. As an alternative, the coder now provides a generic style of HDL templates that do not use a clock enable signal for the RAM structures. The generic RAM template implements clock enable with logic in a wrapper around the RAM.
You may want to use the generic RAM style if your synthesis tool does not support RAM structures with a clock enable, and cannot map generated HDL code to FPGA RAM resources. To learn how to use generic style RAM for your design, see the new Getting Started with RAM and ROM in Simulink demo. To open the demo, type the following command at the MATLAB prompt:
hdlcoderramrom
Simulink HDL Coder does not provide a ROM block, but you can easily build one using basic Simulink blocks. The new Getting Started with RAM and ROM in Simulink demo includes an example in which a ROM is built using a Lookup Table block and a Unit Delay block. To open the demo, type the following command at the MATLAB prompt:
hdlcoderramrom
 | Version 1.6 (R2009b) Simulink HDL Coder Software | Version 1.4 (R2008b) Simulink HDL Coder Software |  |
Learn more about Simulink through this collection of videos, articles, technical literature and the Getting Started with Simulink Guide.
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