| Target Support Package™ TC2 | |
Receive and log capture input pin transitions or configure auxiliary pulse width modulator
c280xdspchiplib and c2833xdspchiplib in Target Support Package™ TC2 software
The eCAP block dialog box provides configuration parameters on four tabbed panes:
General—Set the operating mode for the block (whether the block performs eCAP or APWM processes, assign the pin associated, and set the sample time
eCAP—Configure eCAP functions such as prescalar value, capture pin, and mode control
APWM—Configure waveform and duty cycle values for the pulse width modulation capability
Interrupt—Specify when the block posts interrupts
You can add up to four C280x/C2833x eCAP blocks to your model, one block for each capture pin. For example, you can have one block configured for eCAP mode with eCAP1 pin selected and three blocks configured for APWM mode with assigned pins eCAP2, eCAP3, and eCAP4. Or four blocks configured for eCAP mode with each block assigned a different eCAP pin. You cannot assign the same eCAP pin to two eCAP blocks in one model.
The C280x/C2833x eCAP block has optional input and output ports as shown in the following table.
| Port | Description and When the Port is Enabled |
|---|---|
| Input port SI | Synchronization input for input value from software. Enabled when you select Enable software forced counter synchronizing input in either operating mode. |
| Input port RA | One-shot arming starts the one-shot sequence. Enabled when you set the mode control to One shot. |
| Output port TS | When you enable the reset counter, this option resets the capture event counter after capturing the event time stamp. Enabled when you select Enable reset counter after capture event 1 time-stamp. |
| Output port CF | This port reports the status of the capture event. Enabled when you select Enable capture event status flag output. |
| Output port OF | Enabled when you select Enable overflow status flag output. |
Note The outputs of this block can be vectorized. |
When you select eCAP, the block captures and logs pin transitions for each capture unit to a FIFO buffer. When you select APWM, the block generates asymmetric pulse width modulation (APWM) waveforms for driving downstream systems.
The capture unit includes the following features:
One pin for each capture unit. For example, eCAP1, eCAP2, and so on.
Four maskable interrupt flags, one for each capture unit.
Ability to specify the transition detection—rising edge, falling edge, or both edges.
The value you enter here provides the time base for event captures, clocked by the system clock. A phase register is used to synchronize with other counters via the software or hardware forced sync (refer to Enable counter Sync-In mode). This is particularly useful in APWM mode when you need a phase offset between capture modules. Enter the phase offset as an integer from 0 (no offset) to 42949667295 (232) counts.
Select this to enable the TSCTR counter to load from the TSCTR register when the block receives either the SYNC1 signal or a software force event (refer to Enable software-forced counter synchronizing input).
This option provides a convenient software method for synchronizing one or more eCAP time bases.
Select one of the list entries Pass through, CTR=PRD, or Disabled to synchronize with other counters.
Set the sample time for the block in seconds.
To enable the configuration parameters on this pane, select eCAP from the Operating mode list on the General pane.
Prescale the input signal, called a pulse train, by this value. Entering a 0 bypasses the input prescaler, leaving the input capture signal unchanged.
Continuous performs continuous time-stamp captures using a circular buffer to capture events 1 through 4.
One-Shot disables continuous mode and enables the Enable one-shot rearming control via input port option so you can select it.
Select this option to arm the one-shot sequence:
Reset the Mod4 counter to zero.
Unfreeze the Mod4 counter.
Enable capture register loading.
Specifies the number of capture events after which to stop the capture.
Enables a reset after capture event 1 and creates an Output port TS. When you select this option, the eCAP process resets the counters after receiving a capture event 1 time-stamp.
Start the capture event on a Rising edge or Falling edge.
Select the data type of the counter. The list includes integer and unsigned 8-, 16-, and 32-bit data types, double, single, and Boolean.
Output the capture event status flag on the Output port CF. The block outputs a 0 until the event capture. After the event, the flag value is 1.
Select the data type to represent the capture event flag. The list includes integer and unsigned 8-, 16-, and 32-bit data types, double, single, and Boolean.
Output the status of the elements of the FIFO buffer on the Output port OF. After you select this option, set the data type for the flag in Overflow flag data type.
Select the data type to represent the status flag. The list includes integer and unsigned 8-, 16-, and 32-bit data types, double, single, and Boolean.
To enable the configuration parameters on this pane, select APWM from the Operating mode list on the General pane.
Set the units for measuring the waveform period. Clock cycles uses the high-speed peripheral clock cycles of the DSP chip, or Seconds. Changing these units changes the Waveform period value and the Duty cycle value and Duty cycle units selection.
Source from which the waveform period value is obtained. Select Specify via dialog to enter the value in Waveform period or select Input port to use a value from the input port.
Period of the PWM waveform measured in clock cycles or in seconds, as specified in the Waveform period units.
Note The term clock cycles refers to the high-speed peripheral clock on the F2812 chip. This clock is 75 MHz by default because the high-speed peripheral clock prescaler is set to 2 (150 MHz/2). |
Units for the duty cycle. Select Clock cycles or Percentages from the list. Changing these units changes the Duty cycle value, the Waveform period value, and Waveform period units selection.
Source from which the duty cycle for the specific PWM pair is obtained. Select Specify via dialog to enter the value in Duty cycle or select Input port to use a value from the input port.
Ratio of the PWM waveform pulse duration to the PWM waveform period expressed in Duty cycle units.
Set the active level for the output. Choose Active High or Active Low from the list. When you select Active High, the compare value defines the high time. Selecting Active Low directs the compare value to define the low time.
In the following figure, you see the interrupt options when you put the block in eCAP mode by selecting eCAP for Operating mode on the General pane.
Enables capture event 1 as an interrupt source. You can use the C280x/C2833x Hardware Interrupt block to react to this interrupt.
Enables counter overflow as an interrupt source.
The next figure presents the interrupt options when you put the block in APWM mode by selecting APWM for Operating mode on the General pane.
Post an interrupt when the value of the counter is the same as the value of the period register (CTR=PRD).
Post an interrupt when the value of the counter is the same as the value of the compare register (CTR=CMP).
For detailed information about interrupt processing, see TMS320x28xx, 28xxx Enhanced Capture (eCAP) Module Reference Guide, SPRU807B, available at the Texas Instruments™ website.
| C280x/C2833x eCAN Transmit | C280x/C2833x ePWM | |
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