| Target Support Package™ TC2 | |
Configure Event Manager to generate Enhanced Pulse Width Modulator (ePWM) waveforms
c280xdspchiplib and c2833xdspchiplib in Target Support Package™ TC2 software
A C280x/C2833x system contains multiple ePWM modules, each having two PWM outputs. The C280x/C2833x ePWM block lets you configure up to six ePWM modules.
Specify which target ePWM module to use. Possible values are ePWM1 through ePWM6.
Specify the units of the Timer initial period. Choose Clock cycles (the default) or Seconds. The period register is a uint16, a conversion must be done when Timer period units (a double) is set to seconds. For best performance, select Clock cycles. Doing so reduces calculations and round-off errors.
The source from which the timer period is obtained. Select Specify via dialog to enter the value in Timer initial period, or select Input port to use a value from the input port.
The period of the PWM waveform measured in clock cycles or in seconds, as determined by Timer period units.
Note The term clock cycles refers to the Time-base Clock on the C280x/C2833x chip. See the discussion of the TB clock prescaler divider below for an explanation of how the Time-base Clock speed is calculated. |
Specify the counting mode in which to operate. C280x/C2833x PWMs can operate in three distinct counting modes: Up, Down, and Up-Down. The following illustration shows the waveforms that correspond to these three modes:
Specify the source that generates the EPWMxSYNCO signal, if any. The available choices are EPWMxSYNCI or SWFSYNC, CTR=Zero, CTR=CMPB, and Disable (the default).
Select this checkbox to enable the input port.
Determines whether the ePWM module will use a phase offset and, if so, its source. Choices are Specify via dialog, Input port, and Disable (the default).
This parameter appears when Counting Mode is set to Up-Down and Phase offset source is set to Specify via dialog or Input port. The counting direction determines whether the timer counts up from zero, or down from the XXX value to zero, following phase synchronization.
This field appears when you select Specify via dialog in Phase offset source. Enter the counter phase offset value relative to the time-base that is supplying the sync-in signal.
Note For Phase offset value, enter the value in clock cycles, from 0 to 65535. Fractional seconds cannot be used. |
This value, together with the High Speed TB clock prescaler divider value, determine the clock speed of the Time-Base submodule, which provides all event timing for the ePWM. The Time-base Clock's speed (TBCLK) is the result of dividing the system clock speed by the product of the High Speed TB clock prescaler divider (HSPCLKDIV) and the TB clock prescaler divider (CLKDIV) as in the following formula:
TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV)
Because the default values for both the High Speed TB clock prescaler divider and the High Speed TB clock prescaler divider are both 1, the default value of the Time-base Clock is equal to the system clock speed (SYSCLKOUT) of 100 MHz
Choices are 1, 2, 4, 8, 16, 32, 64, and 128.
See the discussion of the TB clock prescaler divider above for an explanation of this value's role in setting the speed of the Time-base Clock. Choices are 1, 2, 4, 6, 8, 10, 12, and 14.
The ePWMA output pane and ePWMB output pane include the same settings, although the default value is different in some cases, as noted .
Select to enable the ePWMA and/or ePWMB output signals for the module that is currently chosen in the General pane. By default, both Enable ePWMxA and Enable ePWMxB are selected for each of the six ePWM modules you can select in the General pane.
Enables a deadband area of no signal overlap between pairs of ePWM output signals. In all cases, this check box is cleared by default.
Specify the units in which the Duty cycle value is expressed: Percentages (the default) or Clock cycles.
Note Using percentages may cause some additional computation time in generated code. This may or may not be noticeable in your application. |
Specify the source from which the pulse width is to be obtained. Choose Specify via dialog (the default) to enter a value in the Duty cycle field, or Input port to use a value from the input port.
This field appears only when you choose Specify via dialog in Duty cycle source. Enter a value that specifies the pulse width, in the units specified in Duty cycle units.
These settings, along with the other remaining settings in the ePWMA output and ePWMB output panes, determine the behavior of the Action Qualifier (AQ) submodule. Based on these settings, the AQ module decides which events are converted into various action types, thereby producing the required switched waveforms of the ePWMxA and ePWMxB output signals.
For each of these four fields, the available choices are Do nothing, Clear, Set, and Toggle.
The default values for these fields vary between the ePWMA output and ePWMB output panes. The following table shows the defaults for each of these panes:
| Action when counter=... | ePWMA output pane | ePWMB output pane |
|---|---|---|
| ZERO | Clear | Do nothing |
| PRD | Do nothing | Set |
| CMPA on CAU | Set | Do nothing |
| CMPA on CAD | Do nothing | Do nothing |
| CMPB on CBU | Do nothing | Clear |
| CMPB on CBD | Do nothing | Do nothing |
For a detailed discussion of the AQ submodule, see the TMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (SPRU791), available on the Texas Instruments™ website.
These four settings determine how the AQ module handles the S/W force event, an asynchronous event initiated by software (CPU) via control register bits.
Compare value reload condition determines if and when the Action-qualifier S/W Force Register is reloaded from a shadow register. Choices are Load on CTR=Zero (the default), Load on CTR=PRD, Load on either, and Freeze.
Enable continuous S/W force input port specifies the source from which the control logic is obtained. This check box is cleared by default. Select this check box to obtain the control logic from the input port
Continuous S/W force logic specifies what type of S/W force logic to use if the continuous S/W force input port is not enabled. Choices are Forcing Disable (the default), Forcing Low, and Forcing High.
Reload condition for S/W force — Choices are Zero (the default), Period, Either period or zero, and Immediate.
Select to enable High Resolution PWM settings. When the effective resolution for conventionally generated PWM is insufficient, you may want to consider High Resolution PWM (HRPWM). The resolution of PWM is normally dependent upon the PWM frequency and the underlying system clock frequency. To address this limitation, HRPWM uses Micro Edge Positioner (MEP) ™ technology to position edges more finely by dividing each coarse system clock. The accuracy of the subdivision is on the order of 150ps. The relationship between one system clock and edge position in terms of MEP steps is shown in the following figure:
Specify loading mode for HRPWM. This selects the time event that loads the CMPAHR shadow value into the active register.
Specify control mode for HRPWM. The MEP can be controlled using duty cycle control from the CMPAHR register, or using phase control from the TBPHSHR register. Rising edge or falling edge should be controlled from the CMPAHR register. For control of both edges, use the TBPHSHR register.
Specify edge of the PWM that is controlled by the micro-edge positioner™ (MEP) logic.
Specify Compare A (High Resolution) register
Select to enable scale factor optimizer (SFO) software. The TI-supplied MEP scale factor optimizer software functions help to determine dynamically the optimum step size for the MEP based on operating temperature and voltage. It is recommended that applications that use the HRPWM feature should use the SFO software.
The Deadband unit pane lets you specify parameters for the Dead-Band Generator (DB) submodule. Since using the DB submodule is not required for generating a deadband in PWM output, this pane is empty by default. The elements of the Deadband unit pane shown in the following image appear only when you select either or both of the Use deadband for ePWMxA or Use deadband for ePWMxB check boxes in the ePWMA output or ePWMB output panes.
Configure the deadband polarity as AH (active high, the default), AL (active low), AHC (active high complementary), or ALC (active low complementary).
Specify the source from which the control logic is to be obtained. Choose Specify via dialog (the default) to enter explicit values, or Input port to use a value from the input port.
This field appears only when you select Use deadband for ePWMxA in the ePWMA output pane. Enter a value from 0 to 1023 to specify a rising edge delay.
This field appears only when you select Use deadband for ePWMxB in the ePWMB output pane. Enter a value from 0 to 1023 to specify a falling edge delay.
Configure ADC Start of Conversion (SOC) by one or both of the ePWMA and ePWMB outputs.
When you select this option, the ePWMA output triggers ADC start of conversion. By default, this check box is cleared (disabled).
When you select Enable ADC start module A, this field specifies the number of events that triggers ADC start of conversion: First event triggers ADC start of conversion with every event (the default), Second event triggers ADC start of conversion with every second event, and Third event triggers ADC start of conversion with every third event.
When you select Enable ADC start module A, this field specifies the counter match condition that triggers an ADC start of conversion event. Choices are CTR=Zero (the default), CTR=PRD, CTRU=CMPA, CTRD=CMPA, CTRU=CMPB, and CTRD=CMPB.
When you select this option, the ePWMB output triggers ADC start of conversion. By default, this check box is cleared (disabled).
When you select Enable ADC start module B, this field specifies the number of events that triggers ADC start of conversion: First event triggers ADC start of conversion with every event (the default), Second event triggers ADC start of conversion with every second event, and Third event triggers ADC start of conversion with every third event.
When you select Enable ADC start module B, this field specifies the counter match condition that triggers an ADC start of conversion event. Choices are CTR=Zero (the default), CTR=PRD, CTRU=CMPA, CTRD=CMPA, CTRU=CMPB, and CTRD=CMPB.
When you select this option, the ePWM output triggers an ePWM interrupt. By default, this check box is cleared.
When you select Enable ePWM interrupt, this field specifies the number of events that trigger the ePWM interrupt: First event triggers ePWM interrupt with every event (the default), Second event triggers ePWM interrupt with every second event, and Third event triggers ePWM interrupt with every third event.
When you select Enable ePWM interrupt, this field specifies the counter match condition that triggers ePWM interrupt. Choices are CTR=Zero (the default), CTR=PRD, CTRU=CMPA, CTRD=CMPA, CTRU=CMPB, and CTRD=CMPB.
The PWM chopper control pane lets you specify parameters for the PWM-Chopper (PC) submodule. The PC submodule uses a high-frequency carrier signal to modulate the PWM waveform generated by the AQ and DB modules.
Select to enable the chopper module. Use of the chopper module is optional, so this check box is cleared by default.
Chopper frequency divider is a prescaler that is used to set the frequency of the chopper clock. The system clock speed is divided by this value to determine the chopper clock frequency. Choose an integer value from 1 to8.
Choose an integer value from 1 to 16 to set the width of the first pulse. Use this feature to provide a high-energy first pulse to ensure hard and fast power switch turn on.
The duty cycles of the second and subsequent pulses are also programmable. Choices are 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, and 87.5%.
The Trip Zone unit pane lets you specify parameters for the Trip-zone (TZ) submodule. Each ePWM module is connected to six TZ signals (TZ1 to TZ6) that are sourced from the GPIO MUX. These signals indicate external fault or trip conditions. Use the settings in this pane to program the EPWM outputs to respond when faults occur.
Specify the source from which the control logic is to be obtained. Choose Specify via dialog (the default) to explicitly enable Trip-zone signals, or Input port to use information from the input port.
Select any of these check boxes to enable the corresponding Trip-zone signal in One-Shot Mode. In this mode, when the trip event is active, the respective action on the EPWMxA/B output is carried out immediately and is latched. The condition remains latched and can only be cleared by the user under software control.
Select any of these check boxes to enable the corresponding Trip-zone signal in Cycle-by-Cycle Mode. In this mode, when the trip event is active, the respective action on the EPWMxA/B output is carried out immediately and is latched. In Cycle-by-Cycle Mode, the condition is automatically cleared when the PWM Counter reaches zero. Therefore, in Cycle-by-Cycle Mode, the trip event is cleared or reset every PWM cycle.
Upon a fault condition, the ePWMxA and/or ePWMxB output can be overridden and forced to one of the following: No action (the default), High, Low, or Hi-Z(High Impedance).
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