| Target Support Package™ TC2 | |
c281xdspchiplib in Target Support Package™ TC2 software
The C281x CAP block sets parameters for the capture units (CAPs) of the Event Manager (EV) module. The capture units log transitions detected on the capture unit pins by recording the times of these transitions into a two-level deep FIFO stack. The capture unit pins can be set to detect rising edge, falling edge, either type of transition, or no transition.
The C281x chip has six capture units — three associated with each EV module. Capture units 1, 2, and 3 are associated with EVA and capture units 4, 5, and 6 are associated with EVB. Each capture unit is associated with a capture input pin.
Note You can have up to two C281x CAP blocks in any one model—one block for each EV module. |
Each group of EV module capture units can use one of two general-purpose (GP) timers on the target board. EVA capture units can use GP timer 1 or 2. EVB capture units can use GP timer 3 or 4. When a transition occurs, the value of the selected timer is stored in the two-level deep FIFO stack.
This block has up to two outputs: a cnt (count) output and an optional, FIFO status flag output. The cnt output increments each time a transition of the selected type occurs. The status flag outputs are
0 — The FIFO is empty. Either no captures have occurred or the previously stored capture(s) have been read from the stack. (The binary version of this flag is 00.)
1 — The FIFO has one entry in the top register of the stack. (The binary version of this flag is 01.)
2 — The FIFO has two entries in the stack registers. (The binary version of this flag is 10.)
3 — The FIFO has two entries in the stack registers and one or more captured values have been lost. This occurs because another capture occurred before the FIFO stack was read. The new value is placed in the bottom register. The bottom register value is pushed to the top of the stack and the top value is pushed out of the stack. (The binary version of this flag is 11.)
Select the Event Manager (EV) module to use:
A — Use CAPs 1, 2, and 3.
B — Use CAPs 4, 5, and 6.
Select to output the status of the elements in the FIFO. The data type of the status flag is uint16.
The type of data to output:
Send 2 elements (FIFO Buffer) — Sends the latest two values. The output is updated when there are two elements in the FIFO, which is indicated by bit 13 or 11 or 9 being sent (CAP x FIFO). If the CAP is polled when fewer than two elements are captures, old values are repeated. The CAP registers are read as follows:
The CAP x FIFO status bits are read and the value is stored in the status flag.
The top value of the FIFO is read and stored in the output at index 0.
The new top value of the FIFO (the previously stored bottom stack value) is read and stored in the output at index 1.
Send 1 element (oldest) — Sends the older of the two most recent values. The output is updated when there is at least one element in the FIFO, which is indicated by any of the bits 13:12, or 11:10, or 9:8 being sent. The CAP registers are read as follows:
The CAP x FIFO status bits are read and the value is stored in the status flag.
The top value of the FIFO is read and stored in the output.
Send 1 element (latest) — Sends the most recent value. The output is updated when there is at least one element in the FIFO, which is indicated by any of the bits 13:12, or 11:10, or 9:8 being sent. The CAP registers are read as follows:
The CAP x FIFO status bits are read and the value is stored in the status flag.
If there are two entries in the FIFO, the bottom value is read and stored in the output. If there is only one entry in the FIFO, the top value is read and stored in the output.
Time between outputs from the FIFO. If new data is not available, the previous data is sent.
Data type of the output data. Available options are auto, double, single, int8, uint8, int16, uint16, int32, uint32, and boolean. The auto option uses the data type of a connected block that outputs data to this block. If this block does not receive any input, auto sets the data type to double.
Note The output of the C281x CAP block can be vectorized. |
The CAP# panes set parameters for individual CAPs. The particular CAP affected by a CAP# pane depends on the EV module you selected:
CAP1 controls CAP 1 or CAP 4, for EV module A or B, respectively.
CAP2 controls CAP 2 or CAP 5, for EV module A or B, respectively.
CAP3 controls CAP 3 or CAP 6, for EV module A or B, respectively.
Select to use the specified capture unit pin.
Type of transition detection to use for this CAP. Available types are Rising Edge, Falling Edge, Both Edges, and No transition.
The target board GP timer to use. CAPs 1, 2, and 3 can use Timer 1 or Timer 2. CAPs 4, 5, and 6 can use Timer 3 or Timer 4.
Clock divider factor by which to prescale the selected GP timer to produce the desired timer counting rate. Available options are none, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128. The resulting rate for each option is shown .
Scaling | Resulting Rate (µs) |
|---|---|
none | 0.01334 |
1/2 | 0.02668 |
1/4 | 0.05336 |
1/8 | 0.10672 |
1/16 | 0.21344 |
1/32 | 0.42688 |
1/64 | 0.85376 |
1/128 | 1.70752 |
Note The above rates assume a 75 MHz input clock. |
Check this check box to post an asynchronous interrupt on CAP#.
| C281x ADC | C281x eCAN Receive | |
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