| Target Support Package™ TC2 | ![]() |
Interrupt Service Routine to handle hardware interrupt on C281x processor
c281xdspchiplib in Target Support Package™ TC2 software
For many systems, an execution scheduling model based on a timer interrupt is not sufficient to ensure a real-time response to external events. The C281x Hardware Interrupt block addresses this problem by allowing for the asynchronous processing of interrupts triggered by events managed by other blocks in the C281x DSP Chip Support Library.
The C281x blocks that can generate an interrupt for asynchronous processing are:
Only one Hardware Interrupt block can be used in a model. To handle multiple interrupts, place a Demux block at the output of the Hardware Interrupt block to direct function calls to the appropriate function-call subsystems.
For details about this block, refer to C281x Hardware Interrupt block in your Embedded IDE Link™ CC documentation.
This block outputs a function call. The size of the function call line equals the number of interrupts the block is set to handle. The block dialog box presents four parameters for each interrupt. These parameters comprise a set of four vectors of equal length. Each interrupt is represented by one element from each parameter (four elements total), one from the same position in each of these vectors.
The following parameters describe each interrupt:
CPU interrupt numbers
PIE interrupt numbers
Task priorities
Preemption flags
Thus, one interrupt is described by a CPU interrupt number, a PIE interrupt number, a task priority, and a preemption flag.
The CPU and PIE interrupt numbers together uniquely specify a single interrupt for a single peripheral or peripheral module. The following table maps CPU and PIE interrupt numbers to these peripheral interrupts. The row numbers are CPU values and the column numbers are the PIE values.
Note The TINT0 (TIMER 0) interrupt is always reserved, and will generate errors if used. |
C281x Peripheral Interrupt Vector Values
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | |
|---|---|---|---|---|---|---|---|---|
| 1 | PDPINTA (EV-A) | PDPINTB (EV-B) | Reserved | XINT1 | XINT2 | ADCINT (ADC) | TINT0 (TIMER 0) | WAKEINT (LPM/WD) |
| 2 | CMP1INT (EV-A) | CMP2INT (EV-A) | CMP3INT (EV-A) | T1PINT (EV-A) | T1CINT (EV-A) | T1UFINT (EV-A) | T1OFINT (EV-A) | Reserved |
| 3 | T2PINT (EV-A) | T2CINT (EV-A) | T2UFINT (EV-A) | T2OFINT (EV-A) | CAPINT1 (EV-A) | CAPINT2 (EV-A) | CAPINT3 (EV-A) | Reserved |
| 4 | CMP4INT (EV-B) | CMP5INT (EV-B) | CMP6INT (EV-B) | T3PINT (EV-B) | T3CINT (EV-B) | T3UFINT (EV-B) | T3OFINT (EV-B) | Reserved |
| 5 | T4PINT (EV-B) | T4CINT (EV-B) | T4UFINT (EV-B) | T4OFINT (EV-B) | CAPINT4 (EV-B) | CAPINT5 (EV-B) | CAPINT6 (EV-B) | Reserved |
| 6 | SPIRXINTA (SPI) | SPITXINTA (SPI) | Reserved | Reserved | MRINT (McBSP) | MXINT (McBSP) | Reserved | Reserved |
| 7 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
| 8 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
| 9 | SCIRXINTA (SCI-A) | SCITXINTA (SCI-A) | SCIRXINTB (SCI-B) | SCITXINTB (SCI-B) | ECAN0INT (CAN) | ECAN1INT (CAN) | Reserved | Reserved |
| 10 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
| 11 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
| 12 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved |
The task priority indicates the relative importance of tasks associated with the asynchronous interrupts. If an interrupt triggers a higher-priority task while a lower-priority task is running, the execution of the lower-priority task is suspended while the higher-priority task is executed. The lowest value represents the highest priority.The default priority value of the base rate task is 40, so the priority value for each asynchronously triggered task must be less than 40 for these tasks to cause the suspension of the base rate task.
The preemption flag determines whether a given interrupt is preemptable. Preemption overrides prioritization. A preemptable task of higher priority can be preempted by a lower priority nonpreemptable task.

Enter a vector of CPU interrupt numbers for the interrupts you want to process asynchronously.
See the table of C281x Peripheral Interrupt Vector Values for a mapping of CPU interrupt number to interrupt names.
Enter a vector of PIE interrupt numbers for the interrupts you want to process asynchronously.
See the table of C281x Peripheral Interrupt Vector Values for a mapping of CPU interrupt number to interrupt names.
Enter a vector of task priorities for the interrupts you want to process asynchronously.
See the discussion of this block's Vectorized Output for an explanation of task priorities.
Enter a vector of preemption flags for the interrupts you want to process asynchronously.
See the discussion of this block's Vectorized Output for an explanation of preemption flags.
Select this check box if you want to be able to test asynchronous interrupt processing in the context of your Simulink® model.
Note Using this check box is the only way you can test asynchronous interrupt processing behavior in Simulink. |
For detailed information about interrupt processing, see TMS320x281x DSP System Control and Interrupts Reference Guide, SPRU078C, available at the Texas Instruments™ website.
C281x SW Int Trigger, C281x Timer, Idle Task
![]() | C281x GPIO Digital Output | C281x PWM | ![]() |
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