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Embedded IDE Link™ VS Pane Options Overrun Indicator and Software-Based Timer |
Use the options in the Select tree under Real-Time Workshop to perform the following configuration tasks.
Determine your processor, either Analog Devices™ or some other processor if you are not using Embedded IDE Link™ VS software.
Configure your build process.
Specify whether to use custom storage classes.
When you select one of the Embedded IDE Link VS system target files, the Embedded IDE Link VS category appears in the Select tree as shown in the following figure.
Clicking Browse opens the Target File Browser where you select vdsplink_grt.tlc as your Real-Time Workshop System target file. When you select your target configuration, Real-Time Workshop® software chooses the appropriate system target file, template make file, and make command. You can also enter the target configuration filename, and the software fills in the Template makefile and Make command selections.
If you are using Real-Time Workshop® Embedded Coder™ software, select the vdsplink_ert.tlc target file in System target file.
Real-Time Workshop software uses template makefiles to generate the makefile for building the executable file. During the automatic build process, MATLAB® issues the make_rtw command. make_rtw extracts information from the template makefile vdsplink_grt.tmf and creates the actual makefile vdsplink.mk. When Real-Time Workshop software compiles the model, it uses the actual makefile to select the compiler to use to generate the compiled code.
When you generate code from your digital signal processing application, select Generate makefile and use the standard command make_rtw as the Make command. In the Build process area in the Real-Time Workshop category, enter make_rtw for the Make command. Parameters you set in this dialog box belong to the model you are building. They are saved with the model and stored in the model file.
When you generate code from a model employing custom storage classes (CSC), clear Ignore custom storage classes. This setting is the default value for Embedded IDE Link VS software and for Real-Time Workshop Embedded Coder software.
When you select Ignore custom storage classes, storage class attributes and signals are affected in the following ways:
Objects with CSCs are treated as if you set their storage class attribute to Auto.
The storage class of signals that have CSCs does not appear on the signal line, even when you select Storage class from Format > Port/Signals Display in your Simulink® menus.
Ignore custom storage classes lets you switch to a processor that does not support CSCs, such as the generic real-time target (GRT), without reconfiguring your parameter and signal objects.
The Generate code only option does not apply to targeting with Embedded IDE Link VS software. To generate source code without building and executing the code on your processor, select Embedded IDE Link VS from the Select tree. Then, under Runtime, select Create_project for Build action.
Two options control HTML report generation during code generation.
After you generate code, this option tells the software whether to generate an HTML report that documents the C code generated from your model. When you select this option, Real-Time Workshop writes the code generation report files in the html subdirectory of the build directory. The top-level HTML report file is named modelname_codegen_rpt.html or subsystemname_codegen_rpt.html. For more information about the report, refer to the online help for Real-Time Workshop. You can also use the following command at the MATLAB prompt to get more information.
docsearch 'Create code generation report'
In the Navigation options, when you select Model-to-code and Code-to-model, your HTML report includes hyperlinks to various features in your Simulink model.
This option directs Real-Time Workshop to open a MATLAB Web browser window and display the code generation report. If you clear this option, you can open the code generation report (modelname_codegen_rpt.html or subsystemname_codegen_rpt.html) manually in a MATLAB Web browser window or in another Web browser.
Real-Time Workshop software uses the Target Language Compiler (TLC) to generate C code from the model.rtw file. The TLC debugger helps you identify programming errors in your TLC code. Using the debugger, you can perform the following actions:
View the TLC call stack.
Execute TLC code line-by-line.
Analyze or change variables in a specified block scope.
When you select Debug from the Select tree, you see the Debug options as shown in the next figure. In this pane, you set options that are specific to the Real-Time Workshop software process and TLC debugging.
For details about using the options in Debug, refer to About the TLC Debugger in your Real-Time Workshop Target Language Compiler documentation.
On the Optimization pane in the Configuration Parameters dialog box, you set options for the code that Real-Time Workshop software generates during the build process. Use these options to tailor the generated code to your needs. Select Optimization from the Select tree on the Configuration Parameters dialog box. The figure shows the Optimization pane when you select the system target file vdsplink_grt.tlc under Real-Time Workshop system target file.
The following options are typically selected for Real-Time Workshop software to provide optimized code generation for common code operations:
Conditional input branch execution
Signal storage reuse
Enable local block outputs
Reuse block outputs
Eliminate superfluous temporary variables (Expression folding)
Loop unrolling threshold
Optimize initialization code for model reference
For more information about using these and the other Optimization options, refer to the Real-Time Workshop documentation.
On the select tree, the Embedded IDE Link VS category provides options in these areas:
Link Automation — Export a handle to your MATLAB workspace.
Code Generation — Configure your code generation requirements, such as enabling real-time task execution profiling.
Project Options — Set build options for your project code generation, including compiler and linker settings.
Runtime — Set options for run-time operations, like the build action.
Processor-in-the-loop (PIL) verification — Enable processor in the loop capability for your project.
When you use Real-Time Workshop software to build a model to an Analog Devices processor, Embedded IDE Link VS software makes a connection between MATLAB software and the VisualDSP++® IDE. MATLAB software represents that connection as an adivdsp object. The properties of the adivdsp object contain information about the IDE instance it refers to, such as the session and processor it accesses. In this pane, the IDE link handle name option instructs Embedded IDE Link VS software to export the adivdsp object created during code generation to your MATLAB workspace with the name you enter. Replace the default name VDSP_obj with your own name for the object to export.
From this category, you select options that define the way your code is generated:
Profile real-time task execution
Inline run-time library functions
To enable the real-time execution profile capability, select Profile real-time task execution. When you select this option, the build process instruments your code to provide performance profiling at the task level. When you run your code, the executed code reports the profiling information in both a graphical presentation and an HTML report form.
To allow you to specify whether the functions generated from blocks in your model are used inline or by pointers, Inline run-time library functions tells the compiler to inline each Signal Processing Blockset™ and Video and Image Processing Blockset™ function. Using inline functions optimizes your code to run more efficiently. However, such optimization requires more memory.
As shown in the following figure, the default setting uses inlining to optimize your generated code.
When you designate a block function as inline, the compiler replaces each call to a block function with the equivalent function code from the static run-time library. If your model use the same block four times, your generated code contains four copies of the function.
While this redundancy uses more memory, inline functions run more quickly than calls to the functions outside the generated code.
Before you run your model as an executable on any processor, configure the Project options for the model. By default, the setting for the project options is Custom, which applies MathWorks™ software specified compiler and linker settings for your generated code.
To let you determine the degree of optimization provided by the Analog Devices optimizing compiler, you enter the optimization level to apply to files in your project. For details about the compiler options, refer to your VisualDSP++ documentation. When you create new projects, Embedded IDE Link VS software sets the optimization to Function(-o2).
To let you specify the options provided by the Analog Devices linker during link time, you enter the linker options as a string. For details about the linker options, refer to your VisualDSP++ documentation. When you create new projects, Embedded IDE Link VS software sets no linker options.
Enter the amount of memory to use for the stack. For more information on memory requirements, refer to Local block outputs on the Optimization pane of the Configuration Parameters dialog box. The block output buffers are placed on the stack until the stack memory is fully allocated. When the stack memory is full, the output buffers go in global memory. Refer to the online Help system for more information about Real-Time Workshop software options for configuring and building models and generating code.
Before you run your model as an executable on any Analog Devices processor, you must configure the run-time options for the model.
By selecting values for the options available, you configure the operation of your model build process and overrun handling.
To specify to Real-Time Workshop software what to do when you click Build, select one of the following options.:
Create_project — Directs Real-Time Workshop software to start VisualDSP++ IDE and populate a new project with the files from the build process. This option offers a convenient way to build projects in VisualDSP++ software.
Archive_library — Directs Real-Time Workshop software to archive the project for this model. Use this option when you plan to use the model in a model reference application. Model reference requires that you archive your VisualDSP++ software projects for models that you use in model referencing.
Build — Builds the executable file, but does not download the file to your processor.
Build_and_execute — Directs Real-Time Workshop software to build, download, and run your generated code as an executable on your processor.
Create_processor_in_the_loop_project — Directs the Real-Time Workshop code generation process to create PIL algorithm object code as part of the project build.
Your selection for Build action determines what happens when you click Build or press Ctrl+B. Your selection tells Real-Time Workshop software at which stage to stop the code generation and build process.
To run your model on the processor, select the default build action, Build_and_execute. Real-Time Workshop software automatically downloads and runs the model on your processor.
Note When you build and execute a model on your processor, the Real-Time Workshop software build process resets the processor automatically. You do not need to reset the board before building models. |
To enable the overrun indicator, choose one of three ways for the processor to respond to an overrun condition in your model:
None — Ignore overruns encountered while running the model.
Print_message — When the processor encounters an overrun condition, it prints a message to the standard output device, stdout.
Call_custom_function — Respond to overrun conditions by calling the custom function you identify in Interrupt overrun notification function.
When you select Call_custom_function from the Interrupt overrun notification method list, you enable this option. Enter the name of the function the processor should use to notify you that an overrun condition occurred. The function must exist in your code on the processor.
Embedded IDE Link VS software includes code that generates interrupts in models that use multiple clock rates. In the following cases, the overrun indicator does not work:
In multirate systems where the rate in the model is not the same as the base clock rate for your model. In such cases, the timer in Embedded IDE Link VS software provides the interrupts for setting the model rate.
In models that do not include ADC or DAC blocks. In such cases, the timer provides the software interrupts that drive model processing.
If you have Real-Time Workshop Embedded Coder software installed and you select the vdsplink_ert.tlc system target file, you can choose to use the processor-in-the-loop (PIL) feature provided by Embedded IDE Link VS software. Selecting Create_processor_in_the_loop_project for the Build action enables the PIL block action option. PIL block action specifies whether Real-Time Workshop software builds the PIL block and downloads the block to the processor.
Choose one of the following three actions for creating a PIL block:
None — Configures model to generate a VisualDSP++ project that contains the PIL algorithm code. Does not build the PIL object code or block. The new project will not compile in VisualDSP++ software.
Create PIL block — Creates a PIL block, places the block in a new model, and then stops without building or downloading the block. The resulting project will not compile in VisualDSP++ IDE.
Create PIL block_build_and_download — Builds and downloads the PIL application to the processor after creating the PIL block. Adds PIL interface code that exchanges data with Simulink software. Use this selection to update the algorithmic code in an existing PIL block in a model.
Your selections affect how you use the resulting PIL block. The following list describes the build process and actions you take based on the PIL block action setting:
When you click Build on the PIL dialog box, the build process adds the PIL interface code to the project and compiles the project in VisualDSP++ IDE.
If you select Create PIL block, you can build manually from the right-click context menu on the PIL block.
After you select Create PIL Block, copy the PIL block into your model to replace the original subsystem. Save the original subsystem in a different model so you can restore in the future. Click Build to build your model with the PIL block in place.
Add the PIL block to your model to use cosimulation to compare PIL results with the original subsystem results. Refer to the demo "Code Generation Workflow"
in the product demos Embedded IDE Link VS
To use the PIL block in a project after you selected None or Create PIL block for Block action when you built the project, click Build followed by Download in the PIL block dialog box.
Although VisualDSP++ software offers standard project configurations, Release and Debug, models you build with Embedded IDE Link VS software use Custom for a custom configuration that provides a third combination of build and optimization.
Project configurations define sets of project build options. When you specify the build options at the project level, the options apply to all files in your project. For more information about the build options, refer to your Analog Devices VisualDSP++ documentation.
The default settings for Custom are the same as the Release project configuration in VisualDSP++ software, except for the compiler options discussed in the next section Default Project Options in Custom. Custom uses different compiler optimization levels to preserve important features of the generated code.
When you create a new project or build a model to your Analog Devices processor, your project and model inherit the build configuration settings from the configuration Custom. The settings in Custom differ from the settings in the default Debug and Release configurations in VisualDSP++ software in the compiler settings.
For the compiler options, Custom uses the Function(-o2) compiler setting. The VisualDSP++ software default Release configuration uses File(-o3), a slightly more aggressive optimization model.
For memory configuration, where Release uses the default memory model that specifies near functions and data, Custom specifies near functions and data—the -ml1 memory model—because some custom hardware might not support far data or aggregate data. Your VisualDSP++ documentation provides complete details on the compiler build options.
You can change the individual settings or the build configuration within VisualDSP++ IDE. Build configuration options that do not appear on these panes default to match the settings for the Release build configuration in VisualDSP++ software.
If you are using vdsplink_ert.tlc as your system target file, Embedded IDE Link VS software supports generating code that is optimized for the processor by using compiler intrinsics and assembly code to replace certain mathematical operator functions. Embedded IDE Link VS software accomplishes this optimization through the Target Function Library (TFL) replacement mechanism that Real-Time Workshop Embedded Coder software provides. TFL replacement requires Real-Time Workshop Embedded Coder software and the embedded real-time target—vdsplink_ert.tlc.
Some code generation stages launch TFL queries. Based on the processor you select, TFL replaces the default Real-Time Workshop software sum and multiply functions and other arithmetic and mathematical operators with processor-specific compiler intrinsics and assembly code functions. For more general information about TFL, look for TFL in the Interface options in Configuring Real-Time Workshop® Code Generation Parameters.
When you enable TFL replacement, Real-Time Workshop Embedded Coder software uses compiler intrinsics and assembly code functions provided by Embedded IDE Link VS software to replace the sums and multiplies in your generated code. The replacement functions provide optimized operations that enable your generated code to run more efficiently and quickly.
TFL replacement does not provide direct feedback when you generate code. To help you review the TFL replacement operators and code, Real-Time Workshop Embedded Coder software provides the TFL Viewer. To start the viewer with all of the available math libraries listed, enter the following command at the MATLAB prompt:
RTW.viewTFL
The viewer enables you to see the content of target function library tables that were created using Real-Time Workshop Embedded Coder software. The following figure shows the TFL viewer displaying the libraries for the Blackfin® 53x processor family. Follow the instructions in the viewer to see the operators and the TFL code associated with each operator.
You use an option in the Configuration Parameters for your model to enable TFL replacement during code generation. Perform the following steps to enable the TFL replacement process when you generate code from a model.
To use the TFL replacement capability when you generate code, you must install Real-Time Workshop Embedded Coder software and select the system target file vdsplink_ert.tlc.
Open the Configuration Parameters for your model by selecting Simulation > Configuration Parameters from the model menu bar.
On the Select tree in the Configuration Parameters dialog box, choose Real-Time Workshop.
Set the System target file to vdsplink_ert.tlc. Use Browse to select the file.
On the Select tree, choose Interface.
From the Target function library list, select the Analog Devices processor family that matches your processor.
Click OK to save your changes and close the dialog box.
With TFL enabled, your generated code uses the TFL replacement libraries provided for your processor.
| Setting Real-Time Workshop® Options for Analog Devices™ Processors | Model Reference and Embedded IDE Link™ VS Software | |
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