DSP Blockset

Multiphase Clock

Generate multiple binary clock signals

Library

• DSP Sources
• Signal Management / Switches and Counters

Description

The Multiphase Clock block generates a sample-based 1-by-N vector of clock signals, where the integer N is specified by the Number of phases parameter. Each of the N phases has the same frequency, f, specified in hertz by the Clock frequency parameter.

The clock signal indexed by the Starting phase parameter is the first to become active, at t=0. The other signals in the output vector become active in turn, each one lagging the preceding signal's activation by 1/(N*f) seconds, the phase interval. The period of the sample-based output is therefore 1/(N*f) seconds.

The active level can be either high (1) or low (0), as specified by the Active level (polarity) parameter. The duration of the active level, D, is set by the Number of phase intervals over which the clock is active. This value, which can be an integer value between 1 and N-1, specifies the number of phase intervals that each signal should remain in the active state after becoming active. The active duty cycle of the signal is D/N.

Examples

Configure the Multiphase Clock block in the model below to generate a 100 Hz five-phase output in which the third signal is first to become active. Use a high active level with a duration of one interval.

The corresponding settings are as follows:

• Clock frequency = 100
• Number of phases = 5
• Starting phase = 3
• Number of phase intervals over which the clock is active = 1
• Active level (polarity) = High (1)

The Scope window below shows the Multiphase Clock block's output for these settings. Note that the first active level appears at t=0 on y(3), the second active level appears at t=0.002 on y(4), the third active level appears at t=0.004 on y(5), the fourth active level appears at t=0.006 on y(1), and the fifth active level appears at t=0.008 on y(2). Each signal becomes active 1/(5*100) seconds after the previous signal.

To experiment further, try changing the Number of phase intervals over which clock is active setting to 3 so that the active-level duration is three phase intervals (60% duty cycle).

Dialog Box

Opening this dialog box causes a running simulation to pause. See Changing Source Block Parameters in the online Simulink documentation for details.

Clock frequency

The frequency of all output clock signals.

Number of phases

The number of different phases, N, in the output vector.

Starting phase

The vector index of the output signal to first become active. Tunable.

Number of phase intervals over which clock is active

The duration of the active level for every output signal. Tunable in simulation, but not in Real-Time Workshop external mode.

Active level

The active level, High (1) or Low (0). Tunable.

Output data type

The output data type. For information on the Logical and Boolean options of this parameter, see Effects of Enabling and Disabling Boolean Support.

Supported Data Types

• Double-precision floating point
• Single-precision floating point
• Fixed point
• Boolean -- The block may output Boolean values depending on the Output data type parameter setting, as described in Effects of Enabling and Disabling Boolean Support. To learn how to disable Boolean output support, see Steps to Disabling Boolean Support.

To learn how to convert your data types to the above data types in MATLAB and Simulink, see Supported Data Types and How to Convert to Them.

See Also

Clock	Simulink
Counter	DSP Blockset
Pulse Generator	Simulink
Event-Count Comparator	DSP Blockset

Also see Creating Signals Using Signal Generator Blocks for how to use this and other blocks to generate signals.

Modified Covariance Method

Multiport Selector