Overview

This section provides an overview of the steps required to develop a VHDL model for use with the MATLAB component of the Link for ModelSim. To program the VHDL component of a Link for ModelSim application, do the following:

  1. Code the VHDL model for MATLAB verification

  2. Compile and debug the VHDL model

  3. Code the test bench MATLAB functions

  4. Place the MATLAB functions on the MATLAB search path


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