Data Type Conversions :: Coding a Link for ModelSim MATLAB Application (Link for ModelSim)

Link for ModelSim

Data Type Conversions

The Link for ModelSim interface converts VHDL entity data to types that apply in the MATLAB environment. To program a MATLAB function for a VHDL model, you must understand the type conversions that pertain to your application. You need to know what type of data is being passed into the function so you know:

What types of conversions are required before and after data is manipulated
What types of conversions are required to return data to ModelSim

The following table summarizes how the Link for ModelSim converts supported VHDL data types to MATLAB types based on whether the type is scalar and composite.

Note Internally, MATLAB indexes array elements by using a column-major numbering scheme, starting with column 1. That is, MATLAB internally stores data elements from the first column first, the second column second, and so on through the last column. This tends to reverse the order of indexes between MATLAB and VHDL. Consider the following VHDL port definition:

PORT (
sta : OUT ARRAY(1 TO 2) OF BIT_VECTOR(1 TO 8););

In VHDL, to access the second element in the seventh column, you specify

sta(2)(7) <= '1'

The MATLAB array indexing equivalent is

iport.sta(7,2) = '1';

Also, VHDL arrays are commonly defined as (0 to n) or (n DOWNTO 0). In such cases, an offset of 1 is applied because MATLAB array indexing always begins at 1.

VHDL-to-MATLAB Data Type Conversions

VHDL Types...	As Scalar Converts to...	As Composite Converts to...
`STD_LOGIC`, `STD_ULOGIC`, and `BIT`	A character that matches the character literal for the desired logic state.
`STD_LOGIC_VECTOR`, `STD_ULOGIC_VECTOR`, `BIT_VECTOR`, `SIGNED`, and `UNSIGNED`		A column vector of characters (as defined above) with one bit per character.
Arrays of `STD_LOGIC_VECTOR`, `STD_ULOGIC_VECTOR`, `BIT_VECTOR`, `SIGNED`, and `UNSIGNED`		An array of characters (as defined above) with a size that is equivalent to the VHDL port size.
`INTEGER` and `NATURAL`	Type `int32`.	Arrays of type `int32` with a size that is equivalent to the VHDL port size.
`REAL`	Type `double`.	Arrays of type `double` with a size that is equivalent to the VHDL port size.
`TIME`	Type `double` for time values in seconds and type `int64` for values representing simulator time increments (see the description of the `'time'` option in Starting the MATLAB Server).	Arrays of type `double` or `int64` with a size that is equivalent to the VHDL port size.
Enumerated types	Character array (string) that contains the MATLAB representation of a VHDL label or character literal. For example, the label `high` converts to `'high'` and the character literal `'c'` converts to `'''c'''`.	Cell array of strings with each element equal to a label for the defined enumerated type. Each element is the MATLAB representation of a VHDL label or character literal. For example, the vector `(one, '2', three)` converts to the column vector `['one'; '''2'''; 'three']`. A user-defined enumerated type that contains only character literals, converts to a vector or array of characters as indicated for the types `STD_LOGIC_VECTOR`, `STD_ULOGIC_VECTOR`, `BIT_VECTOR`, `SIGNED`, and `UNSIGNED`.

Overview of the Steps for Coding a MATLAB Test Bench Function

Naming a MATLAB Test Bench Function

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