Link for ModelSim

Compiling and Debugging the VHDL Model

After you create or edit your VHDL source files, use the ModelSim compiler to compile and debug the code. You have the option of invoking the compiler from menus in the ModelSim graphic interface or from the command line with the vcom command. The following sequence of ModelSim commands create and map design library work and compile the VHDL file modsimrand.vhd.

ModelSim> vlib work
ModelSim> vmap work work
ModelSim> vcom modsimrand.vhd

For more examples, see the Link for ModelSim tutorials. For details on using the ModelSim compiler, see the ModelSim documentation.

Sample VHDL Entity Definition

Coding a MATLAB Test Bench Function