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The focus of this tutorial is the verification of a VHDL implementation of a Manchester receiver. Decoding a Manchester encoded signal presents several challenges, the most prominent of which is clock recovery. The clock is embedded in the received signal and must be extracted to reproduce the original data stream. The figure below shows the Manchester receiver's model design, which is divided into three VHDL entities.
The following table describes the three sections of code.
| I/Q convolver | Samples the received signal and computes the convolution for the inphase (I) and quadrature (Q) waveforms. For each waveform, the computation is implemented as the sum of XOR operations on the sample and decoded waveform received from the state counter. |
| Decoder | Executes a combinatorial circuit that interprets the results of the I/Q convolver. |
| State counter | Generates the I/Q waveforms that are convolved with received signals, taking into account phase errors (lags and leads), as necessary. The phase of the I/Q generator is adjusted to match the incoming Manchester encoded waveform. To accomplish the necessary adjustment, at the beginning of a new cycle, the state counter checks an adjustment value, adj, and then changes the period of the next I/Q cycle. This adjustment value is limited to adding or removing a single clock period from the 16 periods that are nominally used for an I/Q waveform. |
The following timing diagram shows an inphase waveform, quadrature waveform, and the convolved results with no phase error, data lags, and data leads.
The following sections highlight areas of code in each of the three VHDL files that are of interest for a ModelSim and MATLAB test bench. The files are located in the modelsimdemos/vhdl/manchester directory:
| | Setting Up Tutorial Files | VHDL Code for the I/Q Convolver | |
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