The Receiver :: MATLAB and ModelSim Manchester Receiver Tutorial (Link for ModelSim)

A device that receives the encoded bit stream is responsible for decoding the bit stream by extracting the data from the received signal. In most cases, the receiver must retrieve the original data stream by using the encoded signal without any additional information about the transmit clock. This simplifies the communications channel, but means the receiver must overcome the following:

The Manchester receiver component validates the computations performed by a Manchester receiver device that is modeled in VHDL and simulated in ModelSim. Numerous approaches are available for implementing a Manchester receiver. The model for this tutorial uses a Delay Lock Loop (DLL) that requires the receiver to use a clock that is very close in frequency to the transmit clock. This results in a simple clock recovery circuit that has a limited frequency lock range.

The receiver clock over-samples the received data stream at 16 times the rate of the transmitter clock. Thus, the receiver clock must have a nominal period of 1/16th the data period of the transmitter clock. To compensate for minor differences between the transmitter and receiver clocks or drifts in the channel delay, the receiver clock adjusts its data period by up to one receive clock (+/-) per data period. Thus, the receiver clock can use 15, 16, or 17 cycles to recover the data encoded in the incoming sampled signal. For example, when the receiver clock is slightly faster than the transmitter clock (frequency error), the receiver clock occasionally needs to add an extra receive clock to compensate.

Large sudden phase errors, such as those that occur at startup time, require multiple data periods to acquire a good lock on the signal. By limiting the maximum phase correction to 1/16th of the total data period, the receiver can be slow to correct large phase errors.

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