Link for ModelSim

VHDL Code for the I/Q Convolver

After setting up a design library, typically, you would use the ModelSim Editor to create and modify your VHDL code. For this tutorial, open and examine the existing file iqconv.vhd. This section highlights areas of code in iqconv.vhd that are of interest for a ModelSim and MATLAB test bench:

1. Start ModelSim from MATLAB by issuing a call to the MATLAB vsim function.

2. In ModelSim, change your current directory to the /vhdl/manchester subdirectory you created in Setting Up Tutorial Files. If you set up the files elsewhere, adjust the path accordingly.

   ModelSim> cd C:/MyPlayArea/vhdl/manchester
   

3. Open iqconv.vhd in the edit window with the edit command, as follows:

   ModelSim> edit iqconv.vhd
   

   ModelSim opens its edit window and displays the VHDL code for iqconv.vhd.

4. Search for ENTITY iqconv. This statement defines the entity iqconv.

   ENTITY iqconv IS
   PORT (
     clk     : IN std_logic ;
     enable  : IN std_logic ;
     reset   : IN std_logic ;
   
     i_wf : IN std_logic ;
     q_wf : IN std_logic ;
     samp : IN std_logic ;
   
     isum : OUT std_logic_vector(4 DOWNTO 0);
     qsum : OUT std_logic_vector(4 DOWNTO 0);
     )
   END iqconv;
   

   You will be verifying this entity in the MATLAB environment. Note the following:

   • The name of the entity is iqconv. The MATLAB server assumes the default name for the corresponding MATLAB function is iqconv.

   • The entity must be defined with a PORT clause that includes at least one port definition. Each port definition must specify a port mode (IN, OUT, or INOUT) and a VHDL data type that is supported by the Link for ModelSim interface. For a list of the supported types, see Coding VHDL Entities for MATLAB Verification.

     The entity iqconv in this example is defined with six input ports — clk, enable, reset, i_wf, q_wf, and samp — of type STD_LOGIC and two output ports — isum and qsum — of type STD_LOGIC_VECTOR. The output ports pass simulation output data out to the MATLAB function for verification. The reset, waveform, and sample data input ports receive signals from the MATLAB function. As you will see in MATLAB Function for the I/Q Convolver the MATLAB function does not use the clock signals.

     Note   Alternatively, the input ports can be driven with the ModelSim force command.

     For more information on coding port entities for use with MATLAB, see Coding VHDL Entities for MATLAB Verification.

5. Browse through the rest of iqconv.vhd. The remaining code defines a behavioral architecture for iqconv that

   1. Performs an XOR on the data with each of the I/Q waveforms generated by the state counter.

   2. Performs the XOR operation.

   3. Clocks the isum and qsum into a register.

   Note   XOR is used here because it is the logic equivalent of multiplying two streams of data that are encoded as -1 and +1. If you replace logic '0' with 1 and logic '1' with 0 in an XOR truth table, the result is a multiple that is the basis of a convolution.

6. Close the ModelSim edit window.

Developing the Manchester Receiver VHDL Code

VHDL Code for the Decoder