Link for ModelSim

VHDL Code for the Decoder

Use the ModelSim Editor to open and examine the existing file decoder.vhd. This section highlights areas of code in decoder.vhd that are of interest for a ModelSim and MATLAB test bench:

1. Start ModelSim, if it is not already running, from MATLAB by issuing a call to the MATLAB vsim function.

2. In ModelSim, change your current directory to the /vhdl/manchester subdirectory you created in Setting Up Tutorial Files. If you set up the files elsewhere, adjust the path accordingly.

   ModelSim> cd C:/MyPlayArea/vhdl/manchester
   

3. Open decoder.vhd in the edit window with the edit command, as follows:

   ModelSim> edit decoder.vhd
   

   ModelSim opens its edit window and displays the VHDL code for decoder.vhd.

4. Search for ENTITY. This statement defines the entity decoder:

   ENTITY decoder IS
   PORT (
     isum   : IN std_logic_vector(4 DOWNTO 0);
     qsum   : IN std_logic_vector(4 DOWNTO 0);
   
     adj    : OUT std_logic_vector (1 DOWNTO 0);
     dvalid : OUT std_logic;
     odata  : OUT std_logic;
     )
   END decoder;
   

   You will verify this entity in the MATLAB environment. Note the following:

   • The name of the entity is decoder. The MATLAB server assumes the name for the corresponding MATLAB function is decoder.

   • The PORT clause for this entity, defines two input ports — isum and qsum — and three output ports — adj, dvalid, and odata. The input ports are 5-bit vectors of type STD_LOGIC_VECTOR that receive signals from the MATLAB function. The output port adj is a 2-bit vector of type STD_LOGIC_VECTOR, and dvalid and odata are of type STD_LOGIC. The output ports pass simulation output data out to the function for verification. For more information on coding port entities for use with MATLAB, see Coding VHDL Entities for MATLAB Verification.

5. Browse through the rest of decoder.vhd. The remaining code defines a behavioral architecture for decoder. The architecture models a combinatorial circuit that translates the results of the I/Q convolver, isum and qsum, at the end of each data receive cycle, into an estimate of the transmitted data and phase error. An adj value of 00 indicates that the waveforms are in phase. Values of 01 and 11 indicate a data lead or lag, respectively.

6. Close the ModelSim edit window.

VHDL Code for the I/Q Convolver

VHDL Code for the State Counter