Link for ModelSim

VHDL Code for the State Counter

Use the ModelSim Editor to open and examine the existing file statecnt.vhd. This section highlights areas of code in statecnt.vhd that are of interest for a ModelSim and MATLAB test bench:

1. Start ModelSim, if it is not already running, from MATLAB by issuing a call to the MATLAB vsim function.

2. In ModelSim, change your current directory to the /vhdl/manchester subdirectory you created in Setting Up Tutorial Files. If you set up the files elsewhere, adjust the path accordingly:

   ModelSim> cd C:/MyPlayArea/vhdl/manchester
   

3. Open statecnt.vhd in the edit window with the edit command, as follows:

   ModelSim> edit statecnt.vhd
   

   ModelSim opens its edit window and displays the VHDL code for statecnt.vhd.

4. Search for ENTITY. This statement defines the entity statecnt:

   ENTITY statecnt IS
   PORT (
     clk    : IN std_logic ;
     enable : IN std_logic ;
     reset  : IN std_logic ;
     adj    : IN std_logic_vector (1 DOWNTO 0);
     sync   : OUT std_logic;
     i_wf   : OUT std_logic;
     q_wf   : OUT std_logic;
     )
   END statecnt;
   

   You will verify this entity in the MATLAB environment. Note the following:

   • The name of the entity is statecnt. The MATLAB server assumes the name for the corresponding MATLAB function is statecnt.

   • The PORT clause for this entity defines four input ports — clk, enable, reset, and adj — and three output ports — sync, i_wf, and q_wf. All ports except adj are of type STD_LOGIC. The input port adj is of type STD_LOGIC_VECTOR and is significant in that it receives data rate adjustments from the decoder that account for phase errors.

     The output ports are of type STD_LOGIC. Port sync represents a data clock that has a nominal frequency of 1/16th of the data period. The ports i_wf and q_wf pass decoded inphase and quadrature waveforms to the I/Q convolver where they are convolved with raw sampled Manchester encoded data.

     For more information on coding port entities for use with MATLAB, see Coding VHDL Entities for MATLAB Verification.

5. Browse through the rest of statecnt.vhd. The remaining code defines a behavioral architecture for statecnt. The architecture defines two signals — state and next_state — that it uses to define a simple state machine. Signals state and next_state are of type state_type, an enumerated type that represents the 17 possible clock cycles. The 17th cycle accounts for data lead phase errors. When a phase is complete, the state signal reaches a DECODE_ME state, which triggers code that

   • Applies the data rate adjustment received from the decoder

   • Synchronizes the data clock with the receiver clock

   • Passes the inphase and quadrature waveforms of the current phase data to the I/Q convolver

6. Close the ModelSim edit window.

VHDL Code for the Decoder

Compiling the Manchester Receiver VHDL Files