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Open and examine the existing file manchester_statecnt.m. This MATLAB function
Declares persistent variables i_wf_vect, q_wf_vec, and ploti for storing data between test bench invocations.
persistent i_wf_vect; persistent q_wf_vect; persistent ploti;
Declares the global variable testisdone. As a global variable, it can be accessed from outside the scope of the test bench.
global testisdone;
Sets up a timing parameter such that the simulator calls back the MATLAB function every 10 nanoseconds (10e-9 seconds).
Sets up the layout for a plot figure window positioning three subplots, axis lines, and labels. The three plots show the waveforms for a long cycle, nominal cycle, and short cycle. As part of this setup, the MATLAB function clears the VHDL entity's reset value, sets its enable value, and sets its adj value to '11' (lag data).
Gets the VHDL entity's inphase and quadrature waveform data.
For each cycle, plots the long, nominal, and short cycle waveforms.
The rest of this section highlights areas of code in manchester_statecnt.m required for MATLAB to verify statecnt.vhd:
Start MATLAB, if it is not already running.
In MATLAB, change your current directory to the directory you created in Setting Up Tutorial Files. If you set up the files elsewhere, adjust the path accordingly.
cd C:/MyPlayArea
Open manchester_statecnt.m in the MATLAB Edit/Debug window. Use the menu option File>Open and double-click the filename manchester_statecnt.m or enter the edit command as follows:
edit manchester_statecnt.m
Look at line 1. This line defines the name and required parameters of the MATLAB function that is to service the entity statecnt:
function [iport,tnext] = manchester_statecnt(oport,tnow,portinfo)
In this case, the function definition:
Names the function manchester_statecnt. Because this name does not match the name of the corresponding VHDL entity, you need to specify the test bench name explicitly later when you register the test bench with ModelSim.
Defines the function with the required input and output parameters. The function uses the
The iport parameter to force values onto signals connected to the VHDL entity's input ports reset, enable, and adj
The tnext parameter to instruct ModelSim to call back the function every 10 nanoseconds
The oport parameter to receive signal values from the entity's output ports i_wf, q_wf, and sync
The tnow parameter to check whether the test bench is complete
For more information on the required MATLAB function parameters, see Setting up Expected Parameters.
Make note of the data types of ports defined for the entity under simulation.
The entity statecnt consists of four input ports clk, enable, reset, and adj and three output ports sync, i_wf, and q_wf. All ports except adj are of type STD_LOGIC. The interface converts the scalar data to a character that matches the character literal for the corresponding enumerated type. The adj port is of type STD_LOGIC_VECTOR. This data is converted to a column vector of characters with one bit per character.
For more information on interface data type conversions, see Data Type Conversions.
Search for tnext =. This assignment statement sets up a timing parameter tnext such that the simulator calls back the MATLAB function every 10 nanoseconds.
Advance one line. Here, the MATLAB function uses the value of tnow or the presence of portinfo to check for the first call from the simulator.
Go to the next line. This assignment statement forces the VHDL entity's reset signal to a cleared state.
Go to the next line. This assignment statement forces the VHDL entity's enable signal to a set state, enabling the clock.
Go to the next line. This assignment statement forces the VHDL entity's adj signal to an initial state of '11', indicating a data lag.
Search for tnow >. Here, the function uses the value of tnow to check whether the test bench is done.
Search for i_wf_vect. This line of code, and the line that follows get the entity's inphase and quadrature waveform data.
Go to the next line. The MATLAB function checks whether the entity's sync signal is set. When this signal is set, the data clock is synchronized with the receiver clock, indicating a phase is complete.
Search for iport.adj. This assignment statement, and the two other adj assignment statements that follow, force the VHDL entity's phase adjustment to the next possible value for the next test cycle.
Browse through the rest of manchester_statecnt.m.
Close the MATLAB Edit/Debug window.
| MATLAB Function for the Decoder | Creating a Manchester Receiver Test Bench Script | ![]() |
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