Link for ModelSim

VHDL Cosimulation

Cosimulate a hardware component by applying input signals to and reading output signals from a VHDL model under simulation in ModelSim

Library

Link for ModelSim

Description

The VHDL Cosimulation block cosimulates a hardware component by applying input signals to and reading output signals from a VHDL model under simulation in ModelSim. You can use this block to model a source or sink device by configuring the block with input or output ports only.

Note   The VHDL Sink and VHDL Source icons in the Link for ModelSim block library are provided for convenience only and map directly to the VHDL Cosimulation block.

Using tabbed panels on the block's dialog box, you can configure the following:

• Block input and output ports that correspond to signals, including internal signals, of a VHDL model and an output sample time

• Type of communication and communication settings to be used for exchanging data between simulators

• Rising-edge or falling-edge clocks to apply to your model

• Tcl commands that you want to run before and after the simulation

The Ports tab provides fields for mapping signals of your VHDL design to input and output ports in your block. The signals that you map can be at any level of the VHDL design hierarchy. Simulink deposits an input port signal on a ModelSim signal at the signal's sample rate. Conversely, Simulink reads an output port signal from a specified ModelSim signal at the Simulink sample rate.

In general, Simulink handles port sample periods as follows:

• If an input port is connected to a signal that has an explicit sample period, based on forward propagation, Simulink applies that rate to the port.

• If an input port is connected to a signal that does not have an explicit sample period, Simulink assigns a sample period that is equal to the least common multiple (LCM) of all identified input port sample periods for the model.

• After Simulink sets the input port sample periods, it applies a user-specified output sample time to all output ports. If you do not specify an output sample time, Simulink applies the fastest input sample period to all output ports.

  The Comm tab specifies the mode of communication to be used between Simulink and ModelSim. If you use TCP socket communication, this tab also provides fields for specifying a socket port and, for remote communication, the host name of the computer running ModelSim.

  You can create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model with the Clocks tab. Simulink attempts to create a clock that has a 50% duty cycle and a predefined phase that is inverted for the falling edge case. If necessary, Simulink degrades the duty cycle, as you approach the resolution limit of the ModelSim simulation, with a worst case duty cycle of 66% for a sample period of T=3.

  The following figure shows a timing diagram that includes rising-edge and falling-edge clocks with a Simulink sample period of T=10 and a ModelSim resolution limit of 1 ns. The figure also shows that given those timing parameters, the clock duty cycle is 50%.

  

  The Tcl tab provides a way of specifying tools command language (Tcl) commands to be executed before and after ModelSim simulates the VHDL component of your Simulink model. The before command field on this tab is particularly useful for simulation initialization and startup operations, but cannot be used to change simulation state.

Dialog Box

The Block Parameters dialog box consists of four tabbed panes of configuration options:

• Ports Tab

• Comm Tab

• Clocks Tab

• Tcl Tab

Ports Tab

Block input ports

Signals of your VHDL model that are to be driven by Simulink. Simulink deposits values on the specified ModelSim signal at the signal's sample rate.

Note   Leave this field blank if you are using the block to model a source device.

Specify each port of interest as a test signal pathname, using ModelSim pathname syntax, and enter one pathname per line. A sample pathname for an input port might be /manchester/samp.

The ports that you map can be at any level of the VHDL design hierarchy.

Note   When you define a block input port, make sure that only one source is set up to force input to that signal. For example, you should avoid defining an input port that has multiple instances. If multiple sources force input to a single signal, your simulation model may produce unexpected results.

Block output ports

Signals of your VHDL model that are to be read by Simulink. Simulink reads an output port signal from the specified ModelSim signal at the Simulink signal's sample rate. You can specify a sample rate or -1 in the Output sample time text field. The value -1 instructs the block to inherit the output sample rate from the input rate.

Note   Leave this field blank to configure a cosimulation sink block.

Specify each port of interest as a test signal pathname, using ModelSim pathname syntax, and enter one pathname per line. A sample pathname for an output port might be /manchester/data.

The ports that you map can be at any level of the VHDL design hierarchy.

Output sample time

The time interval (ticks) between consecutive samples applied to all output ports. The resolution of the time interval is equal to the simulator resolution that is set for ModelSim. To determine the resolution, at the ModelSim prompt, enter echo $resolution or report simulator state. The default for this field depends on how you are using the block.

If the Block Has...	The Default Is...
Input and output ports	-1, inherit the sample time of the signal source
Input ports only (sink)	0, has no impact
Output ports only (source)	2

Comm Tab

ModelSim running on this computer

If selected, the block configuration assumes Simulink and ModelSim are running on the same computer. When both applications run on the same computer, you have the option of using shared memory or TCP sockets for the communication channel between the two applications.

Host name

If Simulink and ModelSim are running on different computers, this text field specifies the host name of the computer that is running your VHDL simulation in ModelSim.

Shared memory

If selected, Simulink and ModelSim use the shared memory for communication. To select this option, you must also select ModelSim running on this computer. For more information on modes of communication, see Modes of Communication.

Port number or service

A valid port number or service for your computer system. For information on choosing TCP socket ports, see Choosing TCP/IP Socket Ports.

Clocks Tab

Rising-edge clocks

One or more rising-edge clocks that drive values to the VHDL signals that you are modeling, using the deposit method. Specify each clock as a signal pathname, using ModelSim pathname syntax, and enter one pathname per line. A sample pathname for a clock might be /manchester/clk. You can include the ModelSim simulator prefix sim:, but it is not required.

Falling-edge clocks

One or more falling-edge clocks that drive deposit values to the VHDL signals that you are modeling. Specify each clock as a signal pathname, using ModelSim pathname syntax, and enter one pathname per line. A sample pathname for a clock might be /manchester/clk. You can include the ModelSim simulator prefix sim:, but it is not required.

Tcl Tab

Before simulation command

A Tcl command line to be executed before ModelSim simulates the VHDL component of your Simulink model. You can specify multiple commands by appending each command with a semicolon (;), the standard Tcl concatenation operator.

Alternatively, you can create a ModelSim DO file that lists Tcl commands and then specify that file with the ModelSim do command as follows:

do mycosimstartup.do

Use of this field can range from something as simple as a one-line echo command to confirm that a simulation is running to a complex script that performs an extensive simulation initialization and startup sequence.

Note   The command string or DO file that you specify for this parameter cannot include commands that load a ModelSim project or modify simulator state. For example, they cannot include commands such as start, stop, or restart.

After simulation command

A Tcl command line to be executed before ModelSim simulates the VHDL component of your Simulink model. You can specify multiple commands by appending each command with a semicolon (;), the standard Tcl concatenation operator.

Alternatively, you can create a ModelSim DO file that lists Tcl commands and then specify that file with the ModelSim do command as follows:

do mycosimcleanup.do

Notes   You can include the quit -f command in an after simulation Tcl command string or DO file to force ModelSim to shut down at the end of a cosimulation session. To ensure that all other after simulation Tcl commands specified for the model have an opportunity to execute, specify all after simulation Tcl commands in a single cosimulation block and place quit at the end of the command string or DO file. With the exception of quit, the command string or DO file that you specify cannot include commands that load a ModelSim project or modify simulator state. For example, they cannot include commands such as start, stop, or restart.

To VCD File