Link for ModelSim

wrapverilog

Apply a VHDL wrapper to a Verilog module

Syntax

wrapverilog <verilog_module>
[-nocompile]

Argument

<verilog_module>

Specifies the Verilog module to which a VHDL wrapper is to be applied. The module you specify must be in a valid ModelSim design library when you issue the command.

-nocompile

Suppresses automatic compilation of the resulting VHDL file, verilog_module_wrap.vhd.

Description

The wrapverilog command applies a VHDL wrapper to the specified Verilog module and then automatically compiles the resulting VHDL file. You can then use your wrapped Verilog module with the Link for ModelSim.

Examples

The following command applies a VHDL wrapper to Verilog module myverilogmod.v and writes the output to myverilogmod_wrap.vhd. The -nocompile option suppresses automatic compilation.

ModelSim> wrapverilog myverilogmod.v -nocompile

vsimulink

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