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Events - Seminars

Model-Based Design for Embedded Signal Processing with Simulink


Seminar Overview

Join us for this free seminar to see new tools for Model-Based Design that accelerate the development of signal processing applications. MathWorks engineers will provide a comprehensive half-day technical overview of modeling, simulation, implementation, and verification of real-world, real-time signal processing systems. We'll cover all aspects of Model-Based Design, including algorithm development; system modeling, advanced filter design techniques, fixed-point system design, bit-true simulation, and automatic scaling; automatic C and HDL (VHDL and Verilog) code generation, and design verification through co-simulation and hardware-in-the-loop testing. The session includes extensive live demonstrations including simulations as well as implementation and verification of embedded signal processing systems on DSP and FPGA hardware to illustrate each concept.

Thank you for your interest in MathWorks Seminars. There are no dates currently scheduled for this Seminar. For more information on our seminars and products contact MathWorks sales or please visit:


Who Should Attend

Engineers and engineering managers responsible for creating and delivering embedded signal processing and communications products, including:

  • ASIC engineers
  • DSP software engineers
  • Electrical engineers
  • FPGA engineers
  • Hardware engineers
  • Project managers
  • System architects/engineers

Seminar Highlights

During this seminar, you will explore how integrated tools from The MathWorks can help you to:

  • Model complex signal processing applications
  • Design, simulate, and prototype complete signal processing systems
  • Use a complete design flow from system simulation to implementation on DSPs and FPGAs
Agenda
8:00
Registration/Continental Breakfast
8:30
Welcome & Introductions
8:40
  • Model-Based Design of Signal Processing Systems
  • Digital Filter Design and Implementation
  • Floating and Fixed-Point System Components
10:00
Break
10:15
  • Implement and verify designs on DSPs
  • Implement and verify designs in FPGAs (and ASICs)
  • Design Partitioning between DSPs and FPGAs

 

11:25
Wrap-up, Questions and Answers

 

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