FPGA Design for Altera Devices with MATLAB and Simulink – Recorded Webinar Series
Learn how to accelerate your FPGA design cycle for Altera® devices using HDL code generation tools from MATLAB® and Simulink®. In these webinars, engineers from MathWorks and Altera demonstrate how VHDL® and Verilog® code generation with MATLAB and Simulink supports these FPGA design tasks:
- Build complete system models in Simulink.
- Refine models for FPGA implementation and verify with system models.
- Apply optimizations for improved performance and reduced FPGA resource usage.
- Verify FPGA design implementations through cosimulation with VHDL and Verilog models and hardware cosimulation using Altera development boards.
Part 1: Introduction to FPGA Design Using MATLAB and Simulink
Part 2: Designing and Developing Pulse Doppler Radars Using FPGAs
Part 3: Verifying Floating-Point IP Cores on FPGAs with MATLAB and Simulink
Applications and Topics Discussed
- Using Altera DSP Builder and HDL Coder (formerly Simulink HDL Coder)
- Building fixed-point and floating-point FPGA design implementations
- Managing VHDL and Verilog code generation in HDL Coder using the HDL Workflow Advisor
- Verifying generated HDL using automatic test bench generation and HDL cosimulation
- Running synthesis, mapping, placement, and routing with Altera Quartus® II from the HDL Workflow Advisor
- HDL Coder™
- HDL Verifier™ (formerly EDA Simulator Link™)
- Phased Array System Toolbox™
- DSP Builder Advanced Blockset (from Altera)