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FPGA Design for Altera Devices with MATLAB and Simulink – Recorded Webinar Series

Learn how to accelerate your FPGA design cycle for Altera® devices using HDL code generation tools from MATLAB® and Simulink®. In these webinars, engineers from MathWorks and Altera demonstrate how VHDL® and Verilog® code generation with MATLAB and Simulink supports these FPGA design tasks:

  • Build complete system models in Simulink.
  • Refine models for FPGA implementation and verify with system models.
  • Apply optimizations for improved performance and reduced FPGA resource usage.
  • Verify FPGA design implementations through cosimulation with VHDL and Verilog models and hardware cosimulation using Altera development boards.

Introduction to FPGA Design Using MATLAB and Simulink (34:44)
Designing and Developing Pulse Doppler Radars Using FPGAs (61:43)
Verifying Floating-Point IP Cores on FPGAs with MATLAB & Simulink (35:04)

Applications and Topics Discussed

  • Using Altera DSP Builder and HDL Coder (formerly Simulink HDL Coder)
  • Building fixed-point and floating-point FPGA design implementations
  • Managing VHDL and Verilog code generation in HDL Coder using the HDL Workflow Advisor
  • Verifying generated HDL using automatic test bench generation and HDL cosimulation
  • Running synthesis, mapping, placement, and routing with Altera Quartus® II from the HDL Workflow Advisor

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Call MathWorks: 508-647-7000