Recorded Webinar: Model-Based Design and FPGA Implementation with Simulink

This recorded webinar introduces Simulink for Model-Based Design in the context of FPGA implementation and verification. Once a design is verified in simulation, we demonstrate the path to HDL implementation including validation and verification tools and techniques.

It presents an edge detection algorithm implementation on Altera Stratix II FPGA.

Webinar attendees will learn how engineers use Simulink for Model-Based Design for:

• Simulating and verifying a complete end-to-end reference model
• Developing an algorithm that matches the reference model
• Converting an algorithm into fixed-point
• Making an algorithm render to hardware implementation
• Co-simulating hand-coded HDL with EDA Simulator Link™ MQ (formerly Link for ModelSim®) Automatically generating HDL code for Altera or Xilinx FPGAs using Altera DSP Builder®, or Xilinx System Generator for DSP®

This presentation also highlights major features of Simulink as applied to signal processing and hardware implementation.

Using Simulink for Model-Based Design can shorten the design cycle of embedded systems and hardware products. By offering a unified environment to explore design tradeoffs, and eventually to implement and verify a design on target hardware, including GPPs, DSPs, and FPGAs, you will be able to design in weeks what normally takes months.