Recorded Webinar: Rapid Design and Implementation of FPGA-Based Digital Down Converter Using MATLAB and Simulink

In this webinar, we will use a radar system design example to demonstrate how MATLAB and Simulink can be used to produce high-performance HDL implementations in Altera® FPGAs and HardCopy® ASICs.

Using this design process, engineers can:

• Model and simulate systems and algorithms in Simulink and explore “what-if” scenarios
• Optimize fixed-point designs and see the effect on system metrics
• Generate highly optimized HDL using Simulink and Altera’s DSP Builder Advanced Blockset and optimized intellectual property (IP) cores
• Specify constraints to design to clock-rate requirements
• Close timing on large designs at 350+ MHz clock rates
• Support multi-channel, polyphase, high-performance DSP data paths and efficiently implement FIR and FFT functions

Who should attend:

• Engineers working with, or considering the use of FPGAs for system implementation for radar, EW/ECM, guidance, and sensor-based applications
• Algorithm developers, system designers, and architects
• Embedded software and hardware engineers
• Engineering management